Electronics > Metrology

Low noise chopper and DIY nV meter

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Well, I missed the boat on the nV design challenge, but I have been working on a nV meter which is at the proof-of-concept stage and thought I would share the design for the benefit of those who are interested. At this stage in testing and writing code, it is more of a DC-accurate LNA, and I will include that block of the schematic as I clean up the rest of it. In the name of getting a handle on how this behaves, I didn't get into charge injection cancellation for the input switching, but as I will explain below, a main motivation of the design is to enable minimal current noise while maintaining low voltage noise and drift. The noise spectral density I measured is 1.2 nV/rtHz, which is flat above 25 mHz, but I suspect some of the apparent 1/f noise is the product of thermal variability. Calculating this out, the 0.1-10 Hz p-p noise is around 22 nV (99.7% probability). I haven't measured thermal drift per se, but the natural experiment of living in an old house with no insulation as winter approaches allows me to put it at <7 nV/K. Again, I suspect that further testing with a fully assembled instrument will bring this number down. With a switching frequency of 330 Hz, the residual offset is about 550 nV, rising to around 670 nV at 990 Hz and 1.2 uV at ca. 5 kHz. The time domain trace I've attached is centered at ~550 nV, but I subtracted this offset for ease of interpretation. The heat kicked on around 12000s, hence the jump. It is probably mostly thermocouple effects at the meter terminals, which I'll have to shield in the future. The amplifier was shielded more from this, so I wouldn't expect it to react that quickly. In preliminary testing, the gain (1001x or 101x) does not impact the input offset voltage.

I adapted the design from an AC coupled LNA I have been working on and kept the skeleton of the input stage because I know it works. The modulator switches connect the input and feedback alternately between the two inputs of a differential pair, and the demodulator switches connect the outputs of this differential pair to the inverting and non-inverting terminals of an op amp. In itself, this would give a DC-offset square wave with an amplitude equal to gain * Vos of the differential pair and a pulsating input current proportional to Vos * Cin. The average value of this would be Vin * gain. To reduce the AC portion of this, the output is HP filtered and (re)modulated between a pair of integrators that drive a second differential pair that servos the current in each leg of the first one to drive the inputs to the same voltage. This considerably reduces clock feedthrough and input current pulsation.

There are a couple design choices I made whose motivation may not be immediately apparent, so I'll go into a bit more depth on those. The whole system is frequency modulated (I'll call this chopped despite some ambiguity in how this term is used) to avoid a noise penalty of 3 dB in sampled (time modulated or autozeroed) systems. Obviously, we do pay this penalty by using a diff pair rather than a single-ended amplifier, but I have seen a few time-modulated, single-ended designs, and exploring this topology was more interesting to me, so this is where I took the 3 dB hit. The main diff pair uses a pair of PNP BJTs in the "transconductance enhancer" configuration. Because the op amp output is single ended, the op amp has to go outside of the mod/demod block to keep the entire system frequency modulated. As such, the mod/demod block really just serves to attenuate the input offset voltage of the op amp by the differential gain of the long tailed pair. Ditto noise and TCVos, though the former is limited by the noise of the diff pair itself, and the latter is limited by parasitic thermocouples, etc. There is a limit to how far you can push this gain and have the circuit remain stable, which is why the Av=101 at DC divider maintains ~60 dB gain at high frequencies. One can imagine various ways around this, but for me that would have been more design overhead and (probably) complexity. Anyways, the transconductance enhancer helps push that gain as high as is feasible.

It is possible to construct this with a single integrator and an SPST switch, with the base of Q5B tied to GND. This works well with ideal switches in simulation, but it suffers more from the parasitics of actual CMOS switches. To the extent that the sources of U13 are matched with respect to charge injection, with dual integrators, that becomes a common mode term and is attenuated reasonably well by the CMRR of the servo diff pair. The HP filter and the integrators are both two pole filters, to improve rejection of signal frequencies near the switching frequency. Signals or "signals" that are coherent with the clock frequency (e.g., EMI from the clock traces) do lead to a Vos of the input diff pair, but this is modulated up to the clock frequency rather than appearing as a DC term.

Elsewhere in the design (I'll include the full schematics and design files once things are cleaned up), the clock signals originate from an STM32L432 running at 10 MHz (about 1.2 mA current draw). The output of this chopper-stabilized amplifier is fed through a fourth order Butterworth filter with fc=100 Hz using OPA2205A in a Sallen-Key topology. The data captures and FFTs I took were from the output of this filter. This is converted to a differential signal by another OPA2205A for conversion with an LTC2442. The digital output will be transmitted to a PC via UART (through an optoisolator) to USB with an FT230X. The whole thing draws around 32 mA on the positive rail and 27 mA on the negative rail. Also, there is a TMP117 on the board for monitoring temperature. All these elements are populated, but I haven't written the code yet.

Edit: corrected some erroneous values for resistors R41 and R56. Thanks to Kleinstein for catching this.

Quite impressive performance and quite compicated circuit.

I see a slight problem with the offset correction stage around the NPN differential pair / U12. I don't see how the common mode voltage of U12A/U12B is stabilized / defiened. The control loop only uses the differential output. Though small, the input offset of U12A/B can make the common DC level drift away.  As a quick fix one could try a large resistor (e.g. 10 M) in parallel to C56 or C58. This would limit the gain of one side and this way fix the DC level, so that they won't drift away.

There is a slight chance that the time domain signal has  U12A/B drifting and at the jump get one of them to saturation so that one than gets more noise and a stable output.

I would not call the amplifier frequency modulation, but more like alternating offset. It is a little similar in this respect to the amplifier of the Datron 1281 and Keithley 2182, but with the extra offset correction loop. The correction loop is close to US 7,764,118.

Somehow the values for R30/R31 and R56 at the current source look like they belong to different design steps and amplifier working current. R56 suggests a rather low current of some 0.6 mA for the differential stage and R30/R31 want some 5 mA for the JFETs alone. So looks like one set is of by about a factor of 10. With the current values in the PDF plan Q10 and Q12 would be inactive.

Thanks! I will admit, when I turned this on and saw the scope trace converge on zero, I was very surprised. You were right, R56 should be 150R, which I caught during assembly but forgot to update. Also R41 is 22k rather than the 28k7 I had originally, but that's not very important. I changed the schematic in my original post to reflect this. With the 13.65 mA tail current, somewhat less than half goes through the PNPs. The values were optimized for noise, and R32 and R44 were required for stability.

As far as nothing to set the common mode on the Q5 diff pair, I was worried about the same thing, and I don't fully understand why it behaves well, but it does actually seem to stay put, at least on the time scale of hours. If you set the INT_EN signal low, things go haywire very quickly, but when I have probed the bases of NPN pair Q5, they are actually fairly close to GND. You could say this is due to the parallel resistance of the integrator capacitors, which is about 10G, but it behaves well in simulation too. In simulations, I put resistors in parallel with these capacitors before I finalized the design out of fear this would happen, but taming the gain of these integrators that way limits the effectiveness of the offset correction loop. I also don't think the common mode for that pair is set by the finite impedance of the current sink because when I was building up the design in simulation, those current sinks were modeled with ideal current sources. I did simulate a number of scenarios using op amps with much worse Ib and Vos, but with the same op amp (i.e. delta_Vos=0 in simulation), the common mode stays very close to zero. I left one simulation running overnight and was satisfied that things would probably be OK, and if they weren't, I could just delete R47 and tie the base of Q5B to GND. I will have to record some numbers after I have left it on for a while to see if it drives either diff pair transistors or the current sink into saturation to set the CM.

I am pretty confident the jump was the product of the heat coming on, because it happened at 6:30AM, which is exactly when the heat is programmed to turn on. Also the meter is right under the vent, which is not the best, but moving it would mean dealing with the rat's nest of cables back there, so I have resisted. Anyways, just from how fuzzy the trace was after that jump, it looks like some of the LF noise was from air movement around the meter terminals.

The expected drift for the common mode of U12 A/B is very slow. A few ┬ÁV offset from the OP amps with 1/2 s time constant would be some 10 mV/h range drift rate.  So if it starts well, it may be OK for a long time.

Thermal effects can definitely cause noise. Parts that can be sensitve include the gain setting resistors via thermal EMF at the resistors (R2 and R76). Another issue can be filter capacitors like C56, C58. The supply can also have an effect at some areas, with thermal effects on the supply coupling to the output. Also light can be an issue for some parts.

How do you know how well the multiple JFE2140 share current? Are they selected?
I mean the intended noise reduction depends on that. I remember inserting small source resistors into the Keithley 2182A input stage that has two discrete FET pairs.

Regards, Dieter


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