Low noise chopper and DIY nV meter

[CurtisSeizert]

Well, I missed the boat on the nV design challenge, but I have been working on a nV meter which is at the proof-of-concept stage and thought I would share the design for the benefit of those who are interested. At this stage in testing and writing code, it is more of a DC-accurate LNA, and I will include that block of the schematic as I clean up the rest of it. In the name of getting a handle on how this behaves, I didn't get into charge injection cancellation for the input switching, but as I will explain below, a main motivation of the design is to enable minimal current noise while maintaining low voltage noise and drift. The noise spectral density I measured is 1.2 nV/rtHz, which is flat above 25 mHz, but I suspect some of the apparent 1/f noise is the product of thermal variability. Calculating this out, the 0.1-10 Hz p-p noise is around 22 nV (99.7% probability). I haven't measured thermal drift per se, but the natural experiment of living in an old house with no insulation as winter approaches allows me to put it at <7 nV/K. Again, I suspect that further testing with a fully assembled instrument will bring this number down. With a switching frequency of 330 Hz, the residual offset is about 550 nV, rising to around 670 nV at 990 Hz and 1.2 uV at ca. 5 kHz. The time domain trace I've attached is centered at ~550 nV, but I subtracted this offset for ease of interpretation. The heat kicked on around 12000s, hence the jump. It is probably mostly thermocouple effects at the meter terminals, which I'll have to shield in the future. The amplifier was shielded more from this, so I wouldn't expect it to react that quickly. In preliminary testing, the gain (1001x or 101x) does not impact the input offset voltage.

I adapted the design from an AC coupled LNA I have been working on and kept the skeleton of the input stage because I know it works. The modulator switches connect the input and feedback alternately between the two inputs of a differential pair, and the demodulator switches connect the outputs of this differential pair to the inverting and non-inverting terminals of an op amp. In itself, this would give a DC-offset square wave with an amplitude equal to gain * Vos of the differential pair and a pulsating input current proportional to Vos * Cin. The average value of this would be Vin * gain. To reduce the AC portion of this, the output is HP filtered and (re)modulated between a pair of integrators that drive a second differential pair that servos the current in each leg of the first one to drive the inputs to the same voltage. This considerably reduces clock feedthrough and input current pulsation.

There are a couple design choices I made whose motivation may not be immediately apparent, so I'll go into a bit more depth on those. The whole system is frequency modulated (I'll call this chopped despite some ambiguity in how this term is used) to avoid a noise penalty of 3 dB in sampled (time modulated or autozeroed) systems. Obviously, we do pay this penalty by using a diff pair rather than a single-ended amplifier, but I have seen a few time-modulated, single-ended designs, and exploring this topology was more interesting to me, so this is where I took the 3 dB hit. The main diff pair uses a pair of PNP BJTs in the "transconductance enhancer" configuration. Because the op amp output is single ended, the op amp has to go outside of the mod/demod block to keep the entire system frequency modulated. As such, the mod/demod block really just serves to attenuate the input offset voltage of the op amp by the differential gain of the long tailed pair. Ditto noise and TCVos, though the former is limited by the noise of the diff pair itself, and the latter is limited by parasitic thermocouples, etc. There is a limit to how far you can push this gain and have the circuit remain stable, which is why the Av=101 at DC divider maintains ~60 dB gain at high frequencies. One can imagine various ways around this, but for me that would have been more design overhead and (probably) complexity. Anyways, the transconductance enhancer helps push that gain as high as is feasible.

It is possible to construct this with a single integrator and an SPST switch, with the base of Q5B tied to GND. This works well with ideal switches in simulation, but it suffers more from the parasitics of actual CMOS switches. To the extent that the sources of U13 are matched with respect to charge injection, with dual integrators, that becomes a common mode term and is attenuated reasonably well by the CMRR of the servo diff pair. The HP filter and the integrators are both two pole filters, to improve rejection of signal frequencies near the switching frequency. Signals or "signals" that are coherent with the clock frequency (e.g., EMI from the clock traces) do lead to a Vos of the input diff pair, but this is modulated up to the clock frequency rather than appearing as a DC term.

Elsewhere in the design (I'll include the full schematics and design files once things are cleaned up), the clock signals originate from an STM32L432 running at 10 MHz (about 1.2 mA current draw). The output of this chopper-stabilized amplifier is fed through a fourth order Butterworth filter with fc=100 Hz using OPA2205A in a Sallen-Key topology. The data captures and FFTs I took were from the output of this filter. This is converted to a differential signal by another OPA2205A for conversion with an LTC2442. The digital output will be transmitted to a PC via UART (through an optoisolator) to USB with an FT230X. The whole thing draws around 32 mA on the positive rail and 27 mA on the negative rail. Also, there is a TMP117 on the board for monitoring temperature. All these elements are populated, but I haven't written the code yet.

Edit: corrected some erroneous values for resistors R41 and R56. Thanks to Kleinstein for catching this.

[Kleinstein]

Quite impressive performance and quite compicated circuit.

I see a slight problem with the offset correction stage around the NPN differential pair / U12. I don't see how the common mode voltage of U12A/U12B is stabilized / defiened. The control loop only uses the differential output. Though small, the input offset of U12A/B can make the common DC level drift away.  As a quick fix one could try a large resistor (e.g. 10 M) in parallel to C56 or C58. This would limit the gain of one side and this way fix the DC level, so that they won't drift away.

There is a slight chance that the time domain signal has  U12A/B drifting and at the jump get one of them to saturation so that one than gets more noise and a stable output.

I would not call the amplifier frequency modulation, but more like alternating offset. It is a little similar in this respect to the amplifier of the Datron 1281 and Keithley 2182, but with the extra offset correction loop. The correction loop is close to US 7,764,118.

Somehow the values for R30/R31 and R56 at the current source look like they belong to different design steps and amplifier working current. R56 suggests a rather low current of some 0.6 mA for the differential stage and R30/R31 want some 5 mA for the JFETs alone. So looks like one set is of by about a factor of 10. With the current values in the PDF plan Q10 and Q12 would be inactive.

[CurtisSeizert]

Thanks! I will admit, when I turned this on and saw the scope trace converge on zero, I was very surprised. You were right, R56 should be 150R, which I caught during assembly but forgot to update. Also R41 is 22k rather than the 28k7 I had originally, but that's not very important. I changed the schematic in my original post to reflect this. With the 13.65 mA tail current, somewhat less than half goes through the PNPs. The values were optimized for noise, and R32 and R44 were required for stability.

As far as nothing to set the common mode on the Q5 diff pair, I was worried about the same thing, and I don't fully understand why it behaves well, but it does actually seem to stay put, at least on the time scale of hours. If you set the INT_EN signal low, things go haywire very quickly, but when I have probed the bases of NPN pair Q5, they are actually fairly close to GND. You could say this is due to the parallel resistance of the integrator capacitors, which is about 10G, but it behaves well in simulation too. In simulations, I put resistors in parallel with these capacitors before I finalized the design out of fear this would happen, but taming the gain of these integrators that way limits the effectiveness of the offset correction loop. I also don't think the common mode for that pair is set by the finite impedance of the current sink because when I was building up the design in simulation, those current sinks were modeled with ideal current sources. I did simulate a number of scenarios using op amps with much worse Ib and Vos, but with the same op amp (i.e. delta_Vos=0 in simulation), the common mode stays very close to zero. I left one simulation running overnight and was satisfied that things would probably be OK, and if they weren't, I could just delete R47 and tie the base of Q5B to GND. I will have to record some numbers after I have left it on for a while to see if it drives either diff pair transistors or the current sink into saturation to set the CM.

I am pretty confident the jump was the product of the heat coming on, because it happened at 6:30AM, which is exactly when the heat is programmed to turn on. Also the meter is right under the vent, which is not the best, but moving it would mean dealing with the rat's nest of cables back there, so I have resisted. Anyways, just from how fuzzy the trace was after that jump, it looks like some of the LF noise was from air movement around the meter terminals.

[Kleinstein]

The expected drift for the common mode of U12 A/B is very slow. A few µV offset from the OP amps with 1/2 s time constant would be some 10 mV/h range drift rate.  So if it starts well, it may be OK for a long time.

Thermal effects can definitely cause noise. Parts that can be sensitve include the gain setting resistors via thermal EMF at the resistors (R2 and R76). Another issue can be filter capacitors like C56, C58. The supply can also have an effect at some areas, with thermal effects on the supply coupling to the output. Also light can be an issue for some parts.

[dietert1]

How do you know how well the multiple JFE2140 share current? Are they selected?
I mean the intended noise reduction depends on that. I remember inserting small source resistors into the Keithley 2182A input stage that has two discrete FET pairs.

Regards, Dieter

[CurtisSeizert]

Kleinstein - that's a good point. I've got another one that is half done, so I will populate the top of the board without the BMF gain setting resistors that I used and have that be my test case for various modifications. I know I can nail it down with another servo loop, but I feel that may be overdoing it on complexity. Laying out this block while being cognizant of thermal effects and minimizing parasitic capacitances that might lead to instability was a significant task already. I do very much appreciate the time and thought you put into looking at the design; I was excited to test a board and rushed some elements, and I didn't go beyond guess-and-check in simulation to consider how this would work over longer time periods. I also made some dumb mistakes, like tying the active low enable pin of the TMUX1133 modulation switch high, connecting UART TX on the controller to TX on the FT230, etc., that I would have caught had I reviewed the schematic more carefully.

Some additional things I have noted are that the residual offset is much lower without the covers on the shield frames - down in the range of 330 nV with both covers off. Putting each of these back on makes the offset voltage go up quickly - most of the effect happens within a second or two. When both are on (and the UART is idle), the Vos is around 560 nV, and the contribution from each cover is approximately equal. I do most measurements with them on because they serve well as thermal baffles to reduce air movement around the leads of sensitive components, but the noise is surprisingly good with them off, around 10-12 nV spread with the meter at 100 NPLC. The other thing that impacts the Vos, which I did not expect to be as significant as it is, is what code the uC is running. It seems like the most significant thing is how active the UART TX is because the optocoupler LED takes a fair amount of current with all that returning via GND. The GND connection for high and low inputs are parallel to this return path, with high being closer to the device, but they are about 50 mm away. I will have to look into this more, but it would obviously cause problems if activity on that bus were sporadic.

Finally, I did another long capture, this time with the meter terminals shielded. It was colder last night, and I think the periodic signal was cycling of the heater. Note that with the terminals of the meter shielded from airflow, this cycling did not cause the additional "fuzziness" as it appeared to in my previous capture with the meter terminals exposed. The struggle is real in this house with insulation. I can use my thermal camera as a stud finder even if the outside temperature is just a few degrees different. I will need to simultaneously record temperature going forward to make sure this is what's going on.

[CurtisSeizert]

How do you know how well the multiple JFE2140 share current? Are they selected?
I mean the intended noise reduction depends on that. I remember inserting small source resistors into the Keithley 2182A input stage that has two discrete FET pairs.

Regards, Dieter

I did not select the JFETs, but I have previously tested 40 or so of them from two different orders. The matching from ones within the same order is good - with my samples, the spread was around 25 mV within a lot, so the current sharing should be close enough. They are running at around 800 uA drain current per FET, which should be around 7 mS transconductance, so a 25 mV difference between high and low would only equate to around 175 uA spread of drain current. So you would have one FET drawing 11% more than the average and one drawing 11% less, which won't have a big impact on noise, which will vary inversely with the fourth root of drain current in the square-law region. This is not a gamble I would make with any other JFET pair, but I am comfortable doing it with the JFE2140.

[dietert1]

I have been using the 2182A with a DIY low thermal EMF relay scanner and used one input with an internal short to zero the meter once a minute or so in the analysis software, with good results. Similar thermal EMF may occur on other scanner inputs. Getting the last nV isn't easy. Some people use a temperature chamber to put the whole setup inside.

Regards, Dieter

[Kleinstein]

If one really wants one could improve the current sharing with source side resistors for JFET pairs. So 1 resistor per pair, not per transistor. This would not add extra noise, like classical source resistors.

The ground should normally be separate for the critical signal part and the supply. Besides the ground side it may also be via the supply. The way the amplifier is build, it may be somewhat senstive to supply variations (e.g. with the resistor from the +5 V to the cascode base, or at the loop for the folded cascode.

If really needed one could use a constant current for the OK and then shorten out the LED of the OK with FET to turn it off.

One could probably use considerably larger resistors for R39 / R43 / R55 and this way make the offset correction loop lower gain at the BJT pair and to compensate use smaller resistors for the R48/R50. Chances are one could also get away with a non AZ OP for U12. Chopper stabilized OPs are potential noise sources via EMI I would avoid if reasonable possible. Also an AZ OP-amp with 1 M range resistors at the input is not ideal. I don't see a real need for the relatively expensive SSM2122 transistor pair if the effect on the offset is small.

It looks there is indeed quite some thermal effect. There are many possible source for an offset in the 500 nV range and they can in part compensate. So keeping the lids on is probably good.

[macaba]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

[CurtisSeizert]

If one really wants one could improve the current sharing with source side resistors for JFET pairs. So 1 resistor per pair, not per transistor. This would not add extra noise, like classical source resistors.

The ground should normally be separate for the critical signal part and the supply. Besides the ground side it may also be via the supply. The way the amplifier is build, it may be somewhat senstive to supply variations (e.g. with the resistor from the +5 V to the cascode base, or at the loop for the folded cascode.

If really needed one could use a constant current for the OK and then shorten out the LED of the OK with FET to turn it off.

One could probably use considerably larger resistors for R39 / R43 / R55 and this way make the offset correction loop lower gain at the BJT pair and to compensate use smaller resistors for the R48/R50. Chances are one could also get away with a non AZ OP for U12. Chopper stabilized OPs are potential noise sources via EMI I would avoid if reasonable possible. Also an AZ OP-amp with 1 M range resistors at the input is not ideal. I don't see a real need for the relatively expensive SSM2122 transistor pair if the effect on the offset is small.

It looks there is indeed quite some thermal effect. There are many possible source for an offset in the 500 nV range and they can in part compensate. So keeping the lids on is probably good.

I agree with a lot of those points, especially the lack of need for the SSM2212. I think one of the standard SOT363 rotatable transistor pairs, perhaps the MBT6429, would be appropriate. The influence of that part is negligible, so the exact choice shouldn't matter too much. Regarding the signal GND, I did connect IN- to GND at the FB resistors, but the relay short is connected to GND at the lead of the relay, which puts the two points about 27 mm apart. I probably should have routed IN- through the relay to cancel some of the thermal offset from that, so I will incorporate that in a future revision. At present, it seems that current on GND is the largest individual source of error.

I was somewhat ambivalent about the choice of integrator op amp, and I believe I specified the OPA2186 prior to increasing the integrator resistors to 1M. The OPA2192 would be a better choice at this stage, but the only ones I have of those on hand are MSOP, and the footprint is SOIC.

I have been using the 2182A with a DIY low thermal EMF relay scanner and used one input with an internal short to zero the meter once a minute or so in the analysis software, with good results. Similar thermal EMF may occur on other scanner inputs. Getting the last nV isn't easy. Some people use a temperature chamber to put the whole setup inside.

Regards, Dieter

I'd like to get the ADC working before I put it in a thermal chamber so I can transmit readings and board temperature via USB, but I will ultimately do that testing. A goal with the TMP117 is to be able to do first order temperature compensation so that it's possible to get close without needing extreme temperature stability.

I will keep a list of these things on hand for next revision, but I would really like to implement some sort of charge injection cancellation in that. One of the things I am wondering there is whether a really effective solution exists for integrated switches because the level-shifting is internal. With the TMUX1133 the point where the curve in the datasheet passes through zero is more dependent on signal ground than VSS, but this is only for charge injected at the drain for a given source voltage. With the TMUX6119, they give figures for both directions, and they seem to cross zero around the same point, so using a DAC to set logic ground for the switch with appropriate level shifting may be feasible. I think any way you slice it, a DAC will be necessary, so that is probably the simplest solution. I do get the sense that cancellation down to the ~10 fC  or lower level this way would be quite difficult. Anyways, if anyone has other ideas or lead references, I would appreciate those. Most of the material I have found deals with IC design.

[CurtisSeizert]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

Thanks for the kind words and the helpful suggestion. I will keep updating this thread as I get more results. Ultimately, I will create a github repository for the design files like I did with an AC coupled LNA, but I would like to work out more of the kinks first so that other people seeking to build one of these up aren't saddled with a bunch of troubleshooting.

Regarding the TMUX1133 charge injection, is that point the same for both source and drain charge injection? If I can solve the problem simply by varying the supplies appropriately, that would be ideal.

[Kleinstein]

The charge injection as specified for the switches is for the turn off part. This may be a bit different for the turn on part, though most of the coupling is capacitive of some kind, but possibly with some delays.
There is also simple capacitive coupling from the control signals that depends on the layout. Chances are just a manual trim for the charge injection would be good enough.

For the relay to ground the input, it is not so much about the distance, but possible shared ground and current flowing there.
It would be a good idea to have some EMI filtering at the input. Besides classic EMI it also isolates the amplifier from the source impedance, so that the source impedance has less effect on the charge injection and possibly offset. With chopper stabilized OPs the source impedance can effect both the bias and offset a little.

I totally agree that it makes sense to get the ADC running to simplifiy testing and maybe get extra data (e.g. the 2 switch settings separate).
It can also make sense to have the chopping frequency somewhat in sync with the ADC, possible leaving a short gap just after switching. A separate external DMM may not average all that well over the 2 switch settings. The ADC may be fast enough to actually do the offest correction loop also in the digital domain instead. So use ADC readings to also measure the ripple and than correct with some kind of DAC instead of U12 and fine trim the offset this way.

An interesting point to test may be the input current (e.g. with a low leakage capacitor or just a resistor).

[CurtisSeizert]

The ADC is running. I was being foiled by the fact that the STM32 hardware NCS signal goes high after each chunk of data (max 16 bits with this uC), so I implemented a software NCS signal instead and that is working. The configuration I had planned with the LTC2442 (and what I am currently running) is to use OSR=32768 as the go-to for conversion rate. With a 330 Hz clock (or odd multiples thereof to stay off powerline harmonics), any feedthrough falls in a notch of the sinc4 envelope. ADC conversions are triggered every 57 cycles of the modulator clock to keep that consistent. I attached a quick plot of a handful of values I grabbed from the serial logfile that covers maybe 50s or so. The spread is reasonably tight without having done too much work. With the ADC working, I no longer need to use one of the holes for the input terminals to feed a cable through, so I attached terminals to the front panel and will do some preliminary measurements of input bias current as well as a temperature sweep tomorrow.

The charge injection as specified for the switches is for the turn off part. This may be a bit different for the turn on part, though most of the coupling is capacitive of some kind, but possibly with some delays.
There is also simple capacitive coupling from the control signals that depends on the layout. Chances are just a manual trim for the charge injection would be good enough.

For the relay to ground the input, it is not so much about the distance, but possible shared ground and current flowing there.
It would be a good idea to have some EMI filtering at the input. Besides classic EMI it also isolates the amplifier from the source impedance, so that the source impedance has less effect on the charge injection and possibly offset. With chopper stabilized OPs the source impedance can effect both the bias and offset a little.

I totally agree that it makes sense to get the ADC running to simplifiy testing and maybe get extra data (e.g. the 2 switch settings separate).
It can also make sense to have the chopping frequency somewhat in sync with the ADC, possible leaving a short gap just after switching. A separate external DMM may not average all that well over the 2 switch settings. The ADC may be fast enough to actually do the offest correction loop also in the digital domain instead. So use ADC readings to also measure the ripple and than correct with some kind of DAC instead of U12 and fine trim the offset this way.

An interesting point to test may be the input current (e.g. with a low leakage capacitor or just a resistor).

I agree on the input filtering. Right now I just have a bead and a 10 nF cap that can be connected between the input terminals via relay. When I was designing this, I didn't think about the fact that it might be useful to measure things somewhat fast with the ADC, so I have a pair of differential inputs just connected to GND. The LTC2442 isn't all that fast, but at OSR 64 or 128 it would have been possible to get the ripple going into the filter with a 330 Hz clock. I did put a SMB jack on the board for easily measuring the output before filtering. It will be interesting to see if that residual offset is present as ripple. If it is, then it could be possible to do better with dynamic offset correction using a digital implementation of the Vos correction loop. This would be better to do with a fast(ish) ADC than the LTC2442 to make sure the spikes around the switch times aren't being averaged in. That could be pretty interesting, but I'd need to get a uC with more pins.

[Kleinstein]

I don't think it makes that much sense to look at somewhat faster ADC data to see if the chopping really works well. If there are problems / weak points I would mainly expect it at the transients and thus a thing to look at with a scope. For the ADC the question is if one wants to average over multiple whole periodes including the switching, or if one wants to skip a short time with switching. So get seprate readings for each chopper phase and have a short gap in between. With the LTC2442 the short gap is not really an option as the ADC does no look like it supports a sinc1 mode (simple integration).

Another question is than how to handle mains hum: for best suppression here one would want averaging over whole mains periods, like 10 PLC. On the other side one would also want averaging over whole periods of the chopper clock. To get both at the same time one may consider the chopper clock somewhat linked to mains. 330 Hz  as 5.5 x 60 Hz is actually not that bad in this aspect. 6 Samples per second would be 10 PLC and 55 chopper cycles.  The fitler in the ADC (seems to be sinc4) complicates thing even a bit more as one has no simple start stop of integration, but a smooth start / stop. Consecutive values are no longer independent and this complicated the noise estimates: for short times the Allan deviation curve likely looks too good. So a comparison should be based on somewhat longer time data. On the upside there can be good suppresion over larger frequency range, not just the zeros in the response and the exact timing may not be so critical.

The raw data look quite good / low noise, though it can be a bit tricky to estimate the actual noise density with somewhat correlated points.

[CurtisSeizert]

I have some data from an overnight capture of the ADC readings with the familiar cycling of the furnace on display. Unfortunately, by the time I got everything working and put back together, I didn't have the motivation to record temperature. These agree reasonably well with the data from the 3458A as a sanity check. An interesting thing from the warm-up drift is that the residual offset starts much closer to zero, and at turn on it is reasonably close to the difference in offset I get by idling the controller when debugging, this may just be coincidence, but I think it bears mention. I do believe this warmup drift is largely a thermal effect. Power cycling the meter quickly gives much less drift. This points to deficiencies in the layout with respect to minimizing the effect of parasitic thermocouples. I will ultimately get some thermal camera images of the board as it warms up to see if this highlights problem areas. The results of temperature cycling will be informative here as well - my hypothesis at this point is that the cyclic patterns in the overnight captures I have taken so far are due to changing temperature gradients on the board. This is because the shape of the time series plot looks much more like dT/dt than T.

I also attached a picture of the meter with the terminals on and everything. The rear panel battery charger and battery boards are reused from my LNA project (https://github.com/curtisseizert/LowFreqLNA/tree/main). Anecdotally, plugging in the charger doesn't disrupt the readings that much. The layout is pretty tight, but it's still delivering 2.5A from a buck converter through wires, so there is bound to be some EMI from that. In the future, I will take a capture to quantify this effect.

Here's a quick list of characterization and calibration tasks I have planned:
-Gain calibration for the +/-2mV and +/- 20mV ranges
-Vos vs source impedance (resistors with and without parallel capacitors)
-Scope capture of unfiltered input stage output
-Temperature cycling experiments

[Kleinstein]

The initial warm up drift is surprisingly fast, much faster than expected for the general temperature to stabilize on turn on.  It is considerably faster to get stable temperature gradients, especially those over shorter distances. Expecting a dT/dt part is very reasonable.

One may be able to locate sensitive areas by moving a hot probe over the PCB.

The noise performance is really good. For comparison the HP34420 specifies 8 nV_peak to peak for 50 x 10 PLC and thus some 16-20 seconds per reading.

[CurtisSeizert]

I cleaned up the schematics and fixed the errors that necessitated bodges. They are attached below.

Some very preliminary experiments gave me a sense of the input bias current, which is really more of a source impedance induced offset shift. With the input cap (10 nF, C0G) switched in, it's a bit less than 300 pA. Without the cap, it is around 1 nA. There is some potential instability with inductive sources, like op amp buffers, that I will have to look into more. Increasing the feedback capacitance is probably my first step, but a small R-C damper on the input prior to the modulator may be necessary. From my experience in stabilizing a similar input stage with more JFETs, those are the two most consequential levers to pull in such a case, but I am open to other ideas.

[NWerner]

Could you elaborate on the function of Q10/Q12? It looks like some kind of overcurrent protection  These transistors are not included in your LNA so I guess there is a very specific reason to them.

thanks in advance
Norman

[Gerhard_dk4xp]

The URL in #17:

404 - Attachment Not Found
I wanted to post here yesterday, but couldn't b/c of database error.
Sent an email to a moderator, nothing happened.

[CurtisSeizert]

Could you elaborate on the function of Q10/Q12? It looks like some kind of overcurrent protection  These transistors are not included in your LNA so I guess there is a very specific reason to them.

thanks in advance
Norman

These are "transconductance enhancers" (See AoE Ch. 3x.4). The goal here is to increase the diff pair transconductance and gain as much as possible while keeping the loop stable. This is necessary to ensure low offset and drift because the Vos of the ADA4625-1 is not modulated up to the MOD_CLK frequency. As such, the whole offset correction block serves only to attenuate the offset and drift of the ADA4625-1 by a factor of the differential gain of the diff pair. The emitter resistors R32 and R44 are necessary to reduce the gain enough to keep the loop stable. This is also the case with R77 and C118 in the G=101 configuration - the closed loop gain needs to be around 60dB at high frequencies to keep oscillations at bay.

[CurtisSeizert]

I began looking into the impact of modulator frequency on noise and residual offset yesterday in a more systematic way than I had done before. I wrote the code to change the TIM2 counter (when this overflows, it triggers an interrupt - the ADC read is in the ISR) to automatically give the greatest throughput while maintaining an integer number of modulator clock cycles per ADC read. In practice, this gave sample frequencies between 5.69 and 5.879 SPS (5.88 SPS is the maximum read rate of the converter at OSR=32768). I updated the code, and waited for the output to settle for each experiment. Once it looked settled, I pasted the PuTTY scrollback into Excel and checked that it had indeed settled. My criterion for valid data here was abs(first reading - last reading) < 2 sigma, and if that wasn't met, I let it go a bit longer and repeated. It's not ideal, but it's good enough for a forum post.

The two responses I analyzed were residual Vos, which followed a predictable pattern, and noise density. I calculated noise density as sigma/sqrt(bandwidth), which assumes it is white noise. The denominator in all cases is nearly identical, so this is really a surrogate for standard deviation, but it is scaled such that it permits comparison to previous data I had gathered. The key previous data point here is that noise density, as measured post-Butterworth filter on a DMM, was about 1.15 nV/rtHz at a 330 Hz modulator clock frequency. I chose this frequency because it is the least common multiple of 55 Hz (the first sinc4 notch frequency for OSR=32768) and 30 Hz. Here's the data from the ADC:

Freq       Mean  Noise density
149.97   0.43   1.19
149.97   0.42   1.20
165.02   0.42   2.29
180.01   0.42   2.77
210.00   0.42   1.71
330.03   0.43   1.84
330.03   0.42   1.74
990.10   0.46   1.68
2490.04   0.52   1.74
9900.99   0.82   2.17
15151.52   1.04   2.51

Frequency is in Hz, mean is in uV, and noise density is in nV/rtHz. The data are also summarized in the attached graph. The 150 Hz and 330 Hz points were repeated. The order wasn't random, but it wasn't by frequency. The two 150 Hz experiments were actually the first and last runs to control for drift.

It is not clear to me why the ADC noise is so much worse than the DMM sampling at about the same rate for my standard 330 Hz modulator frequency, and I'll investigate this further by getting a spectrum at some of the key points here. The lack of impact on Vos at powerline harmonics (180 Hz) vs between them (such as 150 Hz and 210 Hz) was expected from understanding how the offset correction loop works and simulation. Signals around the modulator frequency lead to an offset between the two inputs of the differential pair (though the frequency response of the HP filters and integrators in the Vos correction loop are meant to minimize this), but this offset is modulated up to the modulator frequency, so it does not appear as a DC offset at the output. This is probably the reason why the noise density with a 180 Hz clock is so much higher - increased ripple at the clock frequency. It may be useful to implement a synchronous filter in a later revision to better reject this ripple. That said, the anomaly at 330 Hz (wrt to DMM results) means some caution might be warranted in interpreting the calculated noise densities here; there could be other factors at play. Anyways, the absence of rectification of signals that are coherent with the clock frequency is one of the useful features of this topology. This makes it less sensitive to crosstalk from the clock lines, at least with respect to offset. Coherent signals that are modulated faster than the settling time of the filter will cause problems, but this could also be solved by adding a synchronous filter.

Having gotten what I thought was an optimum clock frequency for measuring drift, etc. with a minimum of noise, I put the box into a thermal chamber, but I found the loop was not stable when clocked at 150 Hz, especially in the temperature chamber (for some reason). This happened a few times. The Vos would settle then slowly drift up before shooting up to about 16 uV (always about the same value). On occasion, it would jump around a bit and then settle back to a reasonably close Vos with a lot more noise. I checked what had happened, and the CM of the Vos correction diff pair had gone low enough to bring the current sink transistor into saturation. To see if it would fix the issue, I put a 10M resistor in parallel with one of the integrator caps (just one so as not to reduce the gain of the Vos correction loop). I took the opportunity to increase the FB caps to 33 pF. These changes made it more likely to settle back from 16 uV to something different at higher noise, but they didn't prevent the issue. Interestingly, it was stable on the bench at this frequency but not in the thermal chamber. Going back to 330 Hz was necessary to keep everything stable. I attached a plot of this divergence, but I reduced the scale so the increased noise would be apparent.

Edit: Credit to Kleinstein for pointing out the potential CM issue associated with the NPN diff pair.

[Kleinstein]

The type of filter at the ADC can make a difference for the noise. The LTC2442 has a noise BW of some 6 Hz when used with 6 SPS. Classical integration with a SIN1 response would be only 3 Hz BW for 6 SPS. depending on how the DMM is used (in simple AZ mode on most HP meters) it could however also be 6 Hz.

So the LTC2442 may not be such a good choice for the ADC. From the description it looks like the ADC reverses polarity internally for every conversion and thus has to wait for internal settling of the fitler. This gives the extra noise density from uneven weight to different times.  It may still work if there is some analog filtering and than using a rather fast ADC conversion rate and more averaging on the µC side.
Ideally one would like an ADC with minimal bandwidt and this no latency (sinc1 response) and conversions in sync with the chopper. Instead of very slow conversions this could also be fast ones, so that the ADC could measure the 2 switch settings separately and if needed skip the switching glitch part, effectively adding dead time.

[CurtisSeizert]

The type of filter at the ADC can make a difference for the noise. The LTC2442 has a noise BW of some 6 Hz when used with 6 SPS. Classical integration with a SIN1 response would be only 3 Hz BW for 6 SPS. depending on how the DMM is used (in simple AZ mode on most HP meters) it could however also be 6 Hz.

So the LTC2442 may not be such a good choice for the ADC. From the description it looks like the ADC reverses polarity internally for every conversion and thus has to wait for internal settling of the fitler. This gives the extra noise density from uneven weight to different times.  It may still work if there is some analog filtering and than using a rather fast ADC conversion rate and more averaging on the µC side.
Ideally one would like an ADC with minimal bandwidt and this no latency (sinc1 response) and conversions in sync with the chopper. Instead of very slow conversions this could also be fast ones, so that the ADC could measure the 2 switch settings separately and if needed skip the switching glitch part, effectively adding dead time.

It seems like it uses CDS to correct its offset. I had originally thought it was autozeroing because the noise density was close to 1.4 * the DMM measurement. You can get the sampling frequency to be better using the "TWOX" register, which gives a latency of one reading but doubles the throughput. However, it does not look like you can take advantage of this doubled sampling frequency unless you drive the oscillator from an external source; in my design I am using the internal oscillator. It does not mention this in the datasheet except that it does not give different values for SPS with and without TWOX when using the internal oscillator. The thing is, when I calculated the noise densities, the numbers I was dividing by were very close to the (square root of the) ENBW listed in the datasheet, so it is not clear that this could be the source of the discrepancy between the ADC and DMM noise values. It is also not clear why this would be significantly affected by the modulator clock, which should be attenuated by >60 dB for all cases based on the filter envelope with OSR=32768. Hopefully I can find a satisfactory answer to these questions, but I am beginning to agree with you that the LTC2442 could be improved. I do like it for proof of concept, nonetheless, because it is very easy to use. I think maybe the AD4032-24 would be a good choice for this application due to its very modest current consumption and good accuracy. I figure it would cost about 1 mA (2 x ADA4805) to drive it relative to the LTC2442. I would like to use something like the AD4134, but it is waay too thirsty.

[Kleinstein]

A way around the extra noise BW from the ADC / DMM can be some analog low pass with a BW of some 10-30 Hz and than using the ADC with a significant higher speed (e.g. 300 SPS). This would however likely mean not getting the 50/60 Hz suppression from the ADC. Alternatively one would need a rather low analog BW. To get good 50/60 Hz suppression with a low ENBW fitler one may need a more accurate external clock. The relatively wide notch comes with the added noise BW.

A fast ADC like the AD4030 comes with it's own can of worms. They need good drivers for the signal and reference. Poor drivers can effect the INL - so the good INL specs depend on the circuit around. The drivers will add quite a bit to the power consumption. The other point is that there will be more EMI from faster and more SPI trafic and the µC is also more buissy. One the upside a faster ADC may allow to use the amplifier in a non chopped mode (if the ripple suppresson part can be switched passive, e.g. easy with the DAC based version) for somewhat faster signals and to add a dead time in the digital domain.

Before thinking more about another ADC one should look at the switching transients with a scope.

[dietert1]

Seems your case is similar to the Keithley 2182A nanovoltmeter. Its lowest range is 10 mV, which means 1 nV is 10 ** -7 of its range.
The lowest range of our Fluke 845A is 1 uV and the Keithley 148 does +/- 10 nV. Both support manual offset adjustment like a scope.

Regards, Dieter

[CurtisSeizert]

Before thinking more about another ADC one should look at the switching transients with a scope.

Good point. The experiments with this take a long time, so it is easy to get ahead of oneself. The capture currently running is 30 h in the temperature chamber to get a feel for the intrinsic drift as the battery discharges. At the moment, that looks to be a key source of drift, probably due to the decreased dissipation in the LDOs as the battery voltage sags. Hence my thinking about SAR ADCs.

[Kleinstein]

I think a faster ADC makes absolutely sense. This would allow to skip some time just after switching to reduce the effect of the settling phase at the cost of only slightly more noise / more averaging time needed. The other point would be doing the VOS corretion digital and having the option to turn the correction off to operate the amplifier in non chopped mode to look at faster signals.

A change in the thermals when the battery drains is perfectly plausible. The thermal can also effect the regulators and this way the voltage.
The circuit as is has a few points where the supply voltage can also have an effect:
The neg supply sets the current through R26 / R27 and R41 provides some current depending on the positive supply. The supply voltage effects the heat at Q9 and Q13.


@dietert:
yes the circuit is similar to the K2182, but with more gain and a little less noise. The Keithley meter also has a noise BW problem with the ADC: it can choose AZ mode for the ADC at the cost of extra noise BW or use the non AZ mode for the ADC and thus add a little drift from the ADC part. AFAIK the AZ mode does not work well with analog filtering, which is a petty.
The FLuke 845 is a different class of instrument: it is made for low leakage and high impedance sources. Alone from the resistors used for protection and filtering it is much higher voltage noise. A 1 µV range looks good, but this is with an analog meter and thus rather limited resolution and no longer stable in the lowest range.

[dietert1]

Let's try once more: The input range of the ADC depends on the reference voltage that can be some volts. The gain is 1000, so probably the nanovoltmeter input range is some mV and 1 nV will be below 1 ppm of the ADC. I think with some more gain and an input range 100 uV the ADC should be less of a limiting factor.

Regards, Dieter

[CurtisSeizert]

The input ranges are +/- 2 and 20 mV. At gain of 1000, the requirement for ADC noise is not particularly stringent. Just hitting 1 nVRMS requires one to have an ENBW of <1 Hz at the ADC, which means averaging will be required. Several commercially available precision ADCs implement some type of autozeroing to keep the NSD flat, and for those that don't, one could use CDS to keep it flat over the range where one is averaging readings.

As for the design, it is similar to the 2182a, but that doesn't implement the Vos correction block using the second diff pair (to my knowledge - I don't have full schematics). This was important to me because it enables one to have a high Ciss without necessitating pre-charge cycles to avoid large switching transients (or some other charge injection mitigation technique). The inputs are at very nearly the same voltage, so the main source of current noise should be charge injection from the TMUX1133. My goal was to have something approaching the performance of the nV preamp reported by a group at PTB(1), and I undertook the design by asking how could one implement something like Jim Williams's servo-offset-stabilized diff pair designs without needing to hook an AZ op amp up to the inputs. By the way, that group reported a design with improved current noise later (2016 I believe), but I don't have the reference handy. It was the same PI.

(1) D. Drung and J.-H. Storm, “Ultralow-noise chopper amplifier with low input charge injection,” IEEE Trans. Instrum. Meas., vol. 60, no. 7, pp. 2347–2352, Jul. 2011.

[CurtisSeizert]

First, I took a 32 hour capture of the instrument in a temperature chamber at 20 C. The reason for the "jump" (this actually happened over a minute or so) at 20ks is not clear, but the general downward trend is consistent with the trend I have noticed of residual offset being correlated with battery voltage. At some point, I will power it with a bench supply in the temperature chamber and see if that downward drift goes away. This supports the notion that periodic signals (time periods in the hour range) in the first captures I showed were due to environmental influences.

I got waveforms and spectra, and there is nothing in the frequency domain that seems to explain the discrepancy between the ADC noise density and the DMM noise density. I am going to guess that Kleinstein will say this is begging for conversions to be done in sync with half clock cycles, and if that's the case, then I agree. The transients settle quickly, but they are not symmetrical with respect to the DC bias voltage, so filtering them out could lead to nonlinearity. Most of the scope captures I took were several averages, so this is not clear from them, but the peak amplitudes of the switching transients are somewhat variable for each polarity. I averaged the settled values for each level from a scope capture (which itself took 10k averages) and they are 179 uV apart at 1000x gain. I have attached a handful of captures to show the waveforms at various nodes.

I probed around and ultimately took a spectrum of one of the ADC inputs, and I believe I figured out why the ADC was giving worse noise than the DMM, and the reason is extremely banal. I put input protection Schottky diodes on the bottom layer and ran the UART lines fairly close to them. The UART was running at 921600 Baud, and f_s for the ADC is 1.8 MHz, so the harmonics were probably aliasing. To fix this, I just ran the UART transaction before getting the data from the ADC (hence 1 cycle latency for output). The line is silent during conversions, and just like that, the noise density went down by more than 30%. My preliminary capture put it at 1.25 nV/rtHz, but I don't think the output was fully settled. This goes without saying, but I should not have routed a data line near an ADC input.

[dietert1]

Can you measure current into the diodes D2 and D3? They could have 100R resistors to Gnd, like R24 and R25. Certainly the MUXes will inject spikes there and asymmetry may cause DC. Such errors are attenuated by the outer feedback loop, but still you want them to be small.

Regards, Dieter

[Kleinstein]

The captured traces show quite fast settling, though with quite some ringing at 2 frequencies. The faster part (some 20 MHz) looks like it is strongest at the Q5 transistors. The collecors ar tightly coupled tot he rest, so it is a bit tricky to slow it down or dampen it seprately. Chances are less gain for Q5  (larger emiter-resistors R39,R43) could help with this. The frequency is that fast that also inductive coupling and LC resonaces may start to become an issue.

There are also quite some spikes at different times - maybe this is the UART or something else, as it looks much less frequent. At least that part should be avoidable.

The residual offset looks relatively small though still detectable (some 0.2 mV range for the output correcponding to 1 µV or 0.1 µV of offset for the FET amplifier depending on the gain used). This should be good enough and I don't think one would need to improve on this.

The capacitor C42 looks quite small, an I am not so sure that capacitance to ground would be right thing there. The input signal to Q8 is more relative to the +5.4 V supply so capacitance to the + supply may make more sense (could still keep C42 as it is small anyway).

[dietert1]

The same applies to C44 and C45. They could rather be 1 nF to increase the snubber time constant from 1 nsec to 100 nsec. And the input side of MUX U6A and U7A could have snubbers, too - maybe in addition to or instead of the diodes D2 and D3.

Regards, Dieter

[Gerhard_dk4xp]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

....
Regarding the TMUX1133 charge injection, is that point the same for both source and drain charge injection? If I can solve the problem simply by varying the supplies appropriately, that would be ideal.

I have tried a similar chopper some years ago using ADG819 / ADG841 as switches.
The charge injection could indeed be minimized by adjusting the supply voltages.
The problem is that the switching levels move also. The CPLD creates the clocks ,
also the delayed ones for the demodulator.

I decided to try EPC GaN Fets with their small absolute capacitances and build
a modulator in a corner of a different board that I had to do anyway. They are called
"power FETs", but are only  0.9 mm * 0.9 mm nekkid chips with 4 solder balls.
The manufacturers layout decal reqires to pull the solder mask ON the perimeter of
the pads. That prompted an email from JLCPCB. I waived that.
The GaN-FETs need > 3.5V gate voltage for low channel resistance; more than 6V
will kill them. The drain side is much more robust, so the drain should point to the
amplifier input.
 
The idea was to check if I could solder them at all. It was unexpectedly easy. Just use
a TINY amount of hot air or the FETs will fly away for good.

I did not test the modulator; it is constantly second winner against my other projects.
The circuit is only half the modulator, there should be 2 more transistors with opposite
clocks to create AC- for the post amplifier input.

[CurtisSeizert]

The captured traces show quite fast settling, though with quite some ringing at 2 frequencies. The faster part (some 20 MHz) looks like it is strongest at the Q5 transistors. The collecors ar tightly coupled tot he rest, so it is a bit tricky to slow it down or dampen it seprately. Chances are less gain for Q5  (larger emiter-resistors R39,R43) could help with this. The frequency is that fast that also inductive coupling and LC resonaces may start to become an issue.

There are also quite some spikes at different times - maybe this is the UART or something else, as it looks much less frequent. At least that part should be avoidable.

The residual offset looks relatively small though still detectable (some 0.2 mV range for the output correcponding to 1 µV or 0.1 µV of offset for the FET amplifier depending on the gain used). This should be good enough and I don't think one would need to improve on this.

The capacitor C42 looks quite small, an I am not so sure that capacitance to ground would be right thing there. The input signal to Q8 is more relative to the +5.4 V supply so capacitance to the + supply may make more sense (could still keep C42 as it is small anyway).

I can't guarantee the faster ringing is not a probing artifact. I was holding two probes against 1 mm diameter test pads at the same time for those, and spring clips for grounding was not an option. Note that the Q5B trace is 5 mV/div but that the same ringing is present on the clock signal, though it looks cleaner because the scale is larger. I will check that out when the current experiment is done.

I am not sure the source of the spikes, but the timing is not right for it to be anything with the MCU because it happens in both phases of the clock cycle. The UART and SPI transactions both happen at the beginning of MOD_CLK being low.

The amplitude of the square wave taken at the SMB jack (J18) is 178 uV (allowing for 500 us settling). From observing the warm-up transients a number of times, I think the residual Vos before parasitic thermocouples come into play is very close to this, but this could also be a product of the settling behavior of the Butterworth filter.

C42 at 10 pF was helpful in simulations for improving settling time, and it was much more effective than increasing the size of C48 to increase the integrator time constant for the Op amp CM servo. It has to be small to keep that loop stable. Tying it to Vcc would have been better, but it should be fine for now.

The same applies to C44 and C45. They could rather be 1 nF to increase the snubber time constant from 1 nsec to 100 nsec. And the input side of MUX U6A and U7A could have snubbers, too - maybe in addition to or instead of the diodes D2 and D3.

Regards, Dieter

C45 doesn't act like a snubber, and after I built this up I re-ran simulations without R25 and found it to be unnecessary. This is in contrast to my LNA, which does require resistance in parallel with the integrator capacitor for stability. Anyways, these definitely need to be small to keep the loop stable, at least with the current values of Cf (33 pF now - modified since uploading the schematics). The integrator capacitor is meant to cancel the the effect of the input capacitance of the op amp. The snubber on the non-inverting input of U5 is to keep the impedances on the output of the diff pair balanced.

Can you measure current into the diodes D2 and D3? They could have 100R resistors to Gnd, like R24 and R25. Certainly the MUXes will inject spikes there and asymmetry may cause DC. Such errors are attenuated by the outer feedback loop, but still you want them to be small.

Regards, Dieter

I have no way of measuring this current directly, but one could infer it from the voltage at those nodes. Putting resistors in series with these could be an option, but I think this would maintly serve to damp any effects of the junction capacitance of the diodes. In simulation, these nodes all stay within 5 mV of ground, but this is with ideal switches to keep simulation times reasonable.

Overall, I have spent a lot of time simulating various iterations of this, and I don't think I left much on the table for improving transient behavior around switching times. That said, I don't really know what I'm doing, so it could be a deficit of imagination on my part. I am not going to say that every value here is optimal, but they were all chosen on purpose. That said, there may be some room to reduce the gain of the offset correction diff pair. I think one could get more mileage from a deglitching filter, converting in sync with each phase of the clock cycle, or both. Both would be ideal for reducing the tension between frequency rejection and settling time requirements for an antialiasing filter.

Finally, I have some preliminary Vos tempco data, but this is still provisional until I can synchronize my TECsource with reading the serial stream of data that the instrument puts out. If the TMP117 were operational, that would also help. Anyways, it's less than +2 nV/K (from ramp slope), though probably closer to +1 nV/K (from settled values at each end of a 10 C ramp). With a +0.1K/min ramp, the displacement during the ramp is on the order of 30 nV, so under all normal use cases, dT/dt would be more important. I think that's a good sign, because it can be addressed more easily with appropriate thermal isolation slots, etc.

[CurtisSeizert]

I have tried a similar chopper some years ago using ADG819 / ADG841 as switches.
The charge injection could indeed be minimized by adjusting the supply voltages.
The problem is that the switching levels move also. The CPLD creates the clocks ,
also the delayed ones for the demodulator.

I decided to try EPC GaN Fets with their small absolute capacitances and build
a modulator in a corner of a different board that I had to do anyway. They are called
"power FETs", but are only  0.9 mm * 0.9 mm nekkid chips with 4 solder balls.
The manufacturers layout decal reqires to pull the solder mask ON the perimeter of
the pads. That prompted an email from JLCPCB. I waived that.
The GaN-FETs need > 3.5V gate voltage for low channel resistance; more than 6V
will kill them. The drain side is much more robust, so the drain should point to the
amplifier input.
 
The idea was to check if I could solder them at all. It was unexpectedly easy. Just use
a TINY amount of hot air or the FETs will fly away for good.

I did not test the modulator; it is constantly second winner against my other projects.
The circuit is only half the modulator, there should be 2 more transistors with opposite
clocks to create AC- for the post amplifier input.

Thanks for the information about the charge injection. I had also considered using the EPC GaN FETs, but the gate leakage in the datasheet was very high, and I didn't want to make a custom board just to test that. I have used their UPC1966 gate driver in 0.4 mm pitch BGA. I had to use a microscope to place it, but with the reflow toaster oven soldering it is no big deal. Still, for fine pitch BGAs, I find myself in a position of really needing a good reason to use them to spec them on a board that I am inevitably going to hand assemble.

[CurtisSeizert]

I did some investigations around current noise in hopes of minimizing it in the next revision. In one experiment, I partially populated a board with a TMUX1133 and some decoupling caps. I powered the chip with a DC supply at 5.5V and connected VSS to the output of my signal generator to see how viable varying the VSS would be for minimizing charge injection from the input switch. I measured charge injection at the drain by tying it to GND with 1k. The two sources were tied together and held at ground potential with 1k as well. Charge injection was minimal here. I don't know if that's because it was faster than the LNA could measure, but most of the disturbance around switching transitions was just due to ground loops in my setup. I tested this by biasing the switch signal high enough that the switch would always be on and got about the same result.

For the whole nV meter, I measured current noise across a 100R resistor with the LNA with and without the input capacitor. I attached two spectra from this and a time domain plot of the switch transition. It is worth noting that both the rising and falling edge of the clock give the same polarity spike. Note that the horizontal scale is 10us/div. I have been messing around with simulation models to see what I can do to improve this. My working hypothesis at the moment is that most of this is coming from the transition spikes applied to the inverting input of the diff pair via the Cgs of the JFETs.

In various simulations I have run, it seems like the demodulator switch is a large source as well with the injected charge mostly travelling from output to input of the differential pair. Buffering the outputs with emitter followers helped a lot for that, as did adding in my estimates of the parasitic capacitances of the nodes in the diff amp. I think it will be important to get the switching transitions as clean as possible to get optimal current noise.

[NWerner]

I am not sure, whether I understand your description correctly but I will add my 2ct nonetheless:

As far as i know, charge injection (unless somehow compensated) is directly influenced
by channel-characteristics -  so that parts with lower rdson exhibit higher charge injection. TMUX1133 is
rather low-ohmic.

charge injection results from accumulation and redistribution of charge at gate and thus heavily
depend on impedance at source, drain and substrate(?). Lots of IC-lvel circuit tricks are used to
not reduce charge injection  but to make it constant. Maybe a JFET shows fundamentally different behaviour.

[CurtisSeizert]

As a quick update, I am in the midst of redesigning the schematic for a second revision, and I have decided on the broad strokes of how everything will be done. The chopping switches will both be PE4140 quad SOI MOSFET arrays. These are designed as RF mixers and have very low parasitic capacitances. This was an idea I got from (Drung 2015), which is a good reference for current noise in choppers. They measured 3 pF from drain to drain. I measured 1.2 pF from gate to drain, but I am not really set up to make measurements of such small capacitances accurately. I haven't been able to find anything about the structure of this particular FET array, but my assumption is that the distinction between drain and source is arbitrary since the bulk is floating. At 9.5 mA drain current, I measured Rds(on) of 6.5 Ohms for my sample, so the Ciss*Rds FOM is much better than any FET or integrated switch I am aware of.

An interesting thing from Drung 2015 is that there will be excess current noise in a chopped amplifier even if there were no charge injection whatsoever. This is because the Johnson noise associated with the switch's resistance puts some variable charge on the chopper's load capacitance, and when the switch changes states, it samples this variable charge. The expression they derive for wideband excess current noise is i_n=sqrt(8*kB*T*C*fc). There is a 1/f term, but it's just to fit experimental data. The spectrum is flat (at 300K) to about 150 mHz.

When I built up a test jig for the PE4140, the SOT23-6 breakout board I mounted it on had a fair amount of capacitance between one gate and drain, so there was a good deal of feedthrough. I found that by varying the high voltage for the gates to compensate for the difference in capacitive coupling, it is possible to nearly eliminate the current spikes at the input terminal. This is the strategy I am going to use for minimizing charge injection, along with careful layout to minimize coupling. Of course, all the gate signals will be bootstrapped as well. For the demodulator, I will also use a PE4140 but reduce the gate swing to about 1.8V.

V_os compensation will happen through a digital control loop so that I can turn it off and not have things go haywire, this necessitates using a SAR ADC for higher speed and low power consumption, which will be the AD4032-24. The scheme I have for driving the ADC at the moment gives me about 2 mA of quiescent current, so the overall power consumption will still be much better than the LTC2442. I'll post the schematic for the revision when I finish it.

Drung, D., Krause, C., "Excess Current Noise in Amplifiers with Switched Input" IEEE Trans. Instrum. Meas., 64, 6, 1455-1459, 2015.

[ArgyllGargoyle]

As you probably know, you can cast this noise expression as the thermal noise of the equivalent resistance of the switched capacitor.

Did you happen to evaluate the gan fets from epc?

[Gerhard_dk4xp]

I'd find that interesting, too.  :-)

BTW I stumbled across that paper from univ Twente:
<     https://ris.utwente.nl/ws/portalfiles/portal/5337827/Klumperink05reduction.pdf       >

It seems that the traps that generate 1/f take some time to come into existence after
switching a transistor ON. That could be a low-hanging fruit in a chopper amplifier.

Gerhard

[ArgyllGargoyle]

Gerhard,
I was hoping you would chime in - can you tell us any more about the epc devices in this context?

[CurtisSeizert]

I didn't try any GaN FETs because the datasheet numbers I saw for gate leakage were too high. I don't know if they were limited by what they could measure, but even their smallest one is listed as having a typical leakage current of 100 nA at Vgs=5V. I believe their devices have a diode between gate and source to prevent Vgs from going significantly below 0 V, so that could be the source of the leakage. The Ciss of the EPC2038 is 7 pF (typical), which is certainly good for a MOSFET, but not as good as the PE4140. On the whole I don't think it compares favorably to the PE4140 for this application. If I am feeling masochistic, maybe I'll make a 0.4 mm pitch BGA breakout board and put it in my next JLC order, but I am not getting my hopes up for reasonable gate leakage.

It seems like the group from PTB tested some other FETs for their current noise investigation but that the results are in the master's thesis of one of the coauthors (Christian Krause), which I was unable to find. I looked around, and there really are not any other FETs I am aware of that are close to the PE4140 (besides the PE4141) for this. Presumably this is because SOI FETs tend to come in the form of ICs, and the other small Si FETs have ESD protection that compromises leakage. The PE4140 is only rated for 100V HBM, so the ESD protection is minimal, which is kind of scary with such a small Ciss. By the way, all JFETs that have a sufficiently low Rds(on) to not compromise the voltage noise of this amplifier have much larger parasitic capacitances.

[Kleinstein]

For the current noise it should not be only about the capacitance of the switch FETs. The input capacitance of the amplifier (e.g. JFE2140) should also matter. As far as understand it this is related to the so called reset noise with a capacitor. When disconnecting a capacitor there is a sqrt(kb*T*C) noise in the charge of the capacitor and thus the corresponding current just before disconnecting and when connecting again to the other side.

So there is a downside in parallel connection of multiple units instead of a bit higher current per JFET.  As the swtching is usually very fast the cascode part may not be effective in reducing the capacitance.

Compared to ready made chopper OP-amps it helps that the chopping frequency can be relatively low. In certain range one could adjust it depending on the needs and balance between current noise and 1/f noise of the JFET stages.

I would not worry that much about the current noise. The current noise would be relevant only with a relatively high source impedance and that would create quite some thermal noise, so that one would not be able to measure in the nV range anyway and would want a different amplifer. Even with a little higher capacitance from standard CMOS switches the current noise is not that large.
The PE4140 still looks interesting.

[CurtisSeizert]

I am not too worried about current noise, but I would like to keep it as low as possible to be able to measure bridges without the noise figure getting excessively high at source impedances of 10k. With the modifications I made to the diff amp, the differential input capacitance in simulation is 37 pF for most of the bandwidth (through 1 GHz). I think the bandwidth of the cascode only needs to be higher than the f_t of the input JFETs to ensure the Miller effect is suppressed for the whole BW, and this appears to be the case at 800 uA/JFET with the HN4C51. That means an effective capacitance of 74 pF for the sake of current noise calculation, which is acceptable. There is an interesting tradeoff here because larger JFETs usually have lower 1/f corners, so you can chop at lower frequency, but the input capacitances are also higher.

It is worth mentioning that the experiment that turned me off of the TMUX1133 was that while I found it was possible to bias the supply voltages for zero charge injection to the source terminals on changing the state of the switch, it was not possible to do the same for the drain (common). That value was not very sensitive to supply voltage bias, and it was consistent with the ca. 3 nA bias current I observed with the whole amplifier at f=330 Hz. This is not to say there aren't other potential analog switches for the input chopper, but I felt compensation would probably be easier with discretes where I have access to the actual gate drive signals. That said, this is clearly not an application that manufacturers have targeted for discrete MOSFETs because most are not suitable, usually because of gate leakage through ESD protection structures (this is generalizing the ones I have looked at, so there may be some good ones I missed).

The other potential solution I considered, which you could use with discretes or ICs, is to essentially do what the 3458 does and use two multiplying DACs to inject charge at the JFET gate nodes in opposition to the charge injected at the input terminal. This is somewhat complicated to implement though, and the correction charge injection is never perfectly coherent with the charge injection being cancelled out. I believe you could go further and attempt to cancel the incoherence of these with a capacitor between the input node and some further correction signal, but that seems like it would be very tricky to get right. It is definitely advantageous to start with a FET requiring the smallest possible gate charge to bring the device into full conduction. With the PE4140 that seems to be small enough to depend more on PCB layout than on the device itself.

[Kleinstein]

For the switching spike and maybe also the input bias current different switches / fets do make sense. The ready made switch chips tend to switch fast (e.g. 200 ns and faster), while the discrete fet switching often gets relatively slow. In the HP3458 this is needed, so that the DAC part for the compensation can follow. A 3 nA bias for the amplifier is indeed not good.
I once did a quick test for a similar type chopper with 74LV4053 switches and there the charge injection was reasonably low. The on resistance may however be a bit on the high side (20 ohm range).

[CurtisSeizert]

I had a test board made to get a better idea of how feasible it would be to minimize average Ib and spikes by individually controlling switching levels with a PE4140-based chopper. On the board there is a transimpedance amplifier to measure current flowing into the input node. I built a couple up with different transimpedance configurations (One used an LTC6240HV with 100M | 6.8pF, the other used an ADA4637-1 with 10M | 2.2 pF, both had 22 pF to ground at the summing node). With both of them I used a trim pot to get the output within 2 uV of ground when it was disconnected from the FET. With the more sensitive amp, I found the gate leakage current to be negligible at all gate voltages (well under 100 fA). By individually adjusting the low voltages for each gate, it was possible to get the average input bias current <10 pA at 1 kHz. I had it in the neighborhood of 1 pA for a while, but it drifted back up to a few pA. This required mV resolution on the gate voltage adjustment. On the board with the faster amp, I got a minimum bias current of about 16 pA.

With both of these, minimizing the bias current required increasing the low voltage so the FET array was not totally off. I haven't determined r_off under these conditions yet, but it's probably in the neighborhood of 1M. I don't see this as a huge issue in the application as the residual offset of the nanovolt amplifier is <1 uV, so that would be <1 pA flowing from the feedback terminal to the input or vice versa. For this test, however, it did mean there was some current flowing in either static position of the switch, probably due to the FET acting as Rg of an inverting op amp with some offset on the summing node being amplified. Subtracting the average of the currents when the switch was in either static position, I was able to get the current due to chopping down to about 5 pA for the ADA4637-1 board. I was sick of messing with switching voltages at this point, but I saw that on both sides of zero, so I think this should be a viable solution.

I have attached a couple scope traces with the ADA4637-1 board to show the switching spikes. The duty cycle of each clock signal is 49.999% in the first and 50% in the second.

Edit: The second trace didn't seem to attach the first time. Added it.

[CurtisSeizert]

I have just finished the schematics for the second revision of the nV meter (attached). There are some things with the MCU that aren't finalized yet since I will probably be writing some of the code while I work on layout, but other than that things are close to finished. There also may be some resistor and capacitor values for non-critical things that I change as I go on.

The general idea is along the lines of the modifications that Kleinstein and others suggested with switch gate drives as I mentioned previously. The modulator and demodulator both use PE4140 quad MOSFETs instead of integrated switches. Unlike the proof of concept version, the Vos correction feedback loop is digital, so chopping can be turned off to measure fast signals. The offset will be calculated from by doing analog to digital conversions in each phase of the clock cycle and the DAC output adjusted to minimize the change in voltage between the two phases. Similarly, there is a relay to set the source impedance to 10k and that can be used to adjust the gate drive voltages to null the input bias current. Each gate drive clock signal is independent, so dead time can be configured separately for both the modulator and demodulator. I have also added an isolated external trigger that can be used to synchronize conversions or chopping cycles to some external clock source.

The ADC driver is certainly more complex in this case than the LTC2442, but the quiescent current draw should be reasonably low (about 3-4 mA depending on whether ADA4807-2 or ADA4805-2 is used as the driving op amp). It is a composite fully differential amp using a THP210 and a pair of fast op amps, which allows a straightforward implementation of CDS in order to null the offset of the ADC/Driver independently of the chopper input stage. Hopefully using an LT5400 will keep gain consistent within a few ppm over the input voltage range. The individual resistor values would need to be 1k or 10k in that case. The chopper stage is largely the same as before with a few modifications to lower input capacitance, minimize feedthrough from the demodulator, and reduce quiescent current draw.

It was important given the lessons from the first revision to reduce power dissipation, so there will be an external module that uses buck converters (probably using LT8608s) and a Cuk converter (haven't decided on the controller) to generate the input voltages for the LDOs on the board from 4S Li cells. The whole digital section runs at 1.8V (save for the isolators, which will run at their minimum of 2.5V) in order to further reduce power consumption. I noted in the proof of concept model that the board was not particularly EMI sensitive as there was no immediate change in offset voltage when I charged the batteries while continuing conversions, so I think a switchers with tight layout and some shielding should be OK.

[Kleinstein]

The circuit looks quite complicated.

The part around U9A is still a bit sensitive to supply noise, as it mixes parts relative to the pos and neg supply and Vcm.
As a more minor point, R82,R83 look rather high: with so little current the emitter follower may not help much.

I don't hing the CD4051 mux chips are strong enough to drive the relays. This is at least a rather unusual way to drive latiching relays.

I don't think one would really need JFETs (Q16-Q19) as low leakage diodes - the BAV199 should be good enough here. This is especially with D15 as an additional leakage path. Usually one should get away without D15, the OP internal diodes and R94 should be enough to protect the OP-amp. It is also a bit unclear what the target is for the input bias / leakage. There is also the comparator part at the very input that could add leakage that is higher than the diode protection.

Similar the target level of protection is a bit unclear.

[CurtisSeizert]

Kleinstein - thanks looking at the schematic. The circuit is indeed quite complicated, but I did not see any obvious places to simplify it while maintaining the functionality. For example, a simpler ADC driver would be nice, but this one should make it possible to implement CDS to zero the ADC/driver offset and keep the NSD flat at low frequencies. Similarly, there are a number of level shifts using difference amplifiers, but I felt that would be the easiest way to implement the gate drive functionality I wanted, and the overall current draw is <2 mA, mostly from quiescent current of the op amps. If you see any obvious places for simplification, let me know.

The CD4051s should be TMUX4051, but I did not change the symbol names (this is necessary for 1.8V logic compatibility). They seemed like they would be fine from a resistance standpoint with 5V relays, but I looked at the maximum ratings, and they probably won't cut it. That block was a bit of an afterthought, and I now realize it would have destroyed itself. I will probably change it to something similar to what I used in the proof of concept version where I used a TMUX1134 (hopefully with a cheaper switch), but I am open to suggestions.

My target for bias current is +/-5 pA at 25 C, but I will settle for 10pA. The TLV1822 has a typical spec of 150 fA, so I don't think two of them should be an issue. You are right that Q17 and Q18 should not be necessary given the 10k resistor to limit current there, so I will probably delete them. I would like the inputs to be able to withstand at least 10V continuous, and I haven't decided what I want to do to ensure this. The window comparator is too slow to be used for transient protection, even if it is driving a FET switch. The absolute max Vgs and Vds for the PE4140 are 4.2V and 3.3V respectively, so it is definitely the most likely failure point. Perhaps it would be best to use back to back MOSFETs in series with IN+ driven by the comparator as well as bootstrapped diodes for transient protection. I looked at some fault protected IC switches for this purpose briefly, but none really fit the bill for pA leakage and low resistance. This is a tough case for robust input protection given the requirement for low source impedance, and I am open to better ideas.

[Kleinstein]

The input protection is indeed a tricky part, especially with the series element to limit the current. One option may be a PTC and than rather robust clamping diodes (e.g. more 1N4007 and not only BAV199). It is still the question if the PTC may cause some thermal EMF error.  At least the one I tested (relatively high resistance THT part) was OK with hardly any extra thermal EMF error.
Another option is back ot back FETs (depl. mode or MOSFETs with OV OK as voltage source - here one needs to be rather careful with temperature gradients as these can cause thermal EMF errors. In my DMM circuit I get an offset of some 500 nV from the protection, which would not be good for a nV meter. For only a low voltage one may get away with a pair (maybe 2 in parallel) low R JFETs as current limit. With no active power consumption one may be able to keep thermal gradients small.

For the circuit one may get away with a simpler ADC driver, without the extra buffers. It is still possible to just start with a bridge instead of the buffers and keep them as an option. It may be enough to limit the supply to the driver instead

For the demodulator part one may get away with a simpler switch, maybe 4053 type that could be directly controlled.

[CurtisSeizert]

I did think about depletion mode MOSFETs, but the ones I am aware of (like the LND150) have excessive rdsON. The PTCs I am aware of are ms time-scale devices, which is something I could cover with the relay. I could couple a switch like the TMUX1121 (or a single SPST) with the window comparator to be able to turn off the input within around 600 ns and clamp any transient in that time to the supply rails for the switch and open the relays at the same time. Presumably a bootstrapped diode clamp of some description could survive such a transient for the ~1 ms it would take to open the relay. Limiting the rise time of the signal with a ferrite bead and a capacitor is a possibility, but making rise times >>1 us is probably not feasible this way. If anyone is aware of a low rds on latch-up proof switch, that would probably be ideal for limiting input current between 1 us and 1 ms.

I was going to use an integrated switch for the demodulator originally, but in simulations, even low charge injection ones (like the ADG1219) led to charge being injected back to the input as well as some ringing. With the +/-1 V gate drive signals I'd be using for the demodulator, the injected charge is only about 4 fC with no deadtime or about 5.5 fC with 100 ns. Given that, I thought it would be easier to just duplicate a block I had already used for the modulator.

It may be possible to skip the drivers and use the THP210. I may put in some jumper footprints to try that. I see a 0.01% settling time of 1.2 us for the THP210 with a 10V jump, so with a much smaller load transient and ~1.7 us to settle that might work.

[Andreas]

I will probably change it to something similar to what I used in the proof of concept version where I used a TMUX1134 (hopefully with a cheaper switch), but I am open to suggestions.

Hmm,

In your design the Inductivity is switched off hard. So I am missing the free wheeling diodes to protect the MUX.
I am usually using (via capacitor) a (high current) port pin of a 5V controller.
E.g. a ATMEGA168P which has around 25-30 Ohms to drive a coil (178 Ohms) of a TQ2SA_L2 relay.
No hard switch off by the capacitor. -> no free wheeling diodes needed.

The downside is that after a switching I have to wait some 100 ms until the capacitor is fully loaded/discharged.

On initialisation of the controller I use the internall pull up resitors to charge the capacitor slowly.
A reconfiguration of the PORT pin to output + LOW level gives a defined state for the relay.

with best regards

Andreas

[Kleinstein]

For the relay swiching I use drivers like 74AC540 and the 5 V coil between 2 such outputs. 74HC with a 6 V supply may be an option too.  It is not ideal with the drive strength, but is just enough for the low power latiching relays (EE2 or FTR1).  When uses as a chain and switching 1 relay at a time it only needs N+1 outputs. The advantage over the capacitor version is less chance for accidently switching on power up / down.

For the protection there are depletion FETs with lower resistance. E.g. BSS159 or BSP135. JFETs like 2SK2145, would be an option too - if needed 2 or 3 in parallel, which is not that bad with the relatively small cases.  Ideally one wants some with a relatively low threshold to get a reasonable low current with not too much resistance.

If the charge injection is a problem, the same / similar switch for the demodulator could be OK, maybe with a simpler (fixed or manual trimmer) setting for the voltages.

[CurtisSeizert]

Andreas - The relay idea I used was bad. It was one of those end of the day/trying to wrap it up things. The digital section here is 1.8V, so really any relay drive is going to require some sort of level shift. I could use the capacitor thing with an SPDT switch, which I have done before, but the ~100ms charge time here could be a deal breaker if switching off a relay within ~1ms is required to keep whatever protection method I use within its SOA. Honestly, my favorite way is using dual LVC gates. At 4.5V, they have sufficient drive to trigger a 3V coil for an Omron G6KU, though a Panasonic 3.6V TXS2A might be a better choice with something like a 74LVC4225A.

Kleinstein - I will look into using the FETs you mentioned. The BSS159 has reasonably low Rds with Vgs = 0V at 3.5R, so putting those back to back would only increase en by about 5% from the case of having the PE4140 as the only source of input resistance, which is acceptable. I am going to start working on component placement for other blocks and circle back to this, but I'll post a revised pdf for the schematic of the input switching and protection when I get there.

[Andreas]

if switching off a relay within ~1ms is required to keep whatever protection method I use within its SOA.

Hello,

this was only a suggestion from my side to keep the effort low.
For the switchoff duration I would calculate minimum 2-4 ms for the typical signal relays.

For the TQ2SA_L2 it needs ~2,2 ms until the anchor movement is done with full reverse polarity during switch off
(without free wheeling diodes).
with free wheeling diodes (I hope you do not rely on the internal diodes of the driver IC) it will last longer.
Datasheet specs are typical 4 ms. (without free wheeling diodes).

with best regards

Andreas

[Kleinstein]

A classical relay is a bit slow for the protection without resistors to limit the current. It can be a secondary thing to prevent thermal problems with the faster protection and than a few ms more should not be that bad.
A reed relay may be a littel faster, but these are non latching and thus permanent heat sources.

For limiting the very fast transients one can use an inductor of a few mH - this is used e.g. in the HP34420 and other nV meters.

[CurtisSeizert]

Andreas - I do appreciate the suggestion and the info on release time. I rigged up a little jig to see how consistent the release time was with the setup I had mentioned, in this case using a 74LVC2G17 with the outputs attached to a TXS2-L-4.5V-1 I had on hand. The one input is attached to Vcc and the common is attached to ground via 100R (Yes, this is probably killing the relay contacts). With this setup, I am consistently getting 1.86-1.88 ms at 5.4V (which I would probably use as I already have that rail available in the design). At Vcc=5V, the release time increases to 1.98-2.00 ms, which is consistent with your data. It has been clicking back and forth at 20 Hz for about 40 minutes at this point, so there don't seem to be any problems with flyback voltages during the brief time between states that the gate becomes high impedance. I attached a capture of the switching trace (at the relay output) and one of the turnoff, showing that the output of the gate does not get driven significantly below 0V. By the way, this continues to work down to 2.5V without any missed transitions, with a release time of about 5.1 ms. The cutoff seems to be around 2.3V.

Kleinstein - You are right that this is too slow to use for protection, so I think I will probably go with a depletion MOSFET pair back to back to limit current. It may be possible to put an inductor on the input to limit rise times with some RC damping on the input, and I will probably do this (or use a FB) with the value based on how quickly I can turn off the FETs.

[CurtisSeizert]

I have decided on an input protection method and completed the schematics for the power supply, so I have attached some updated schematics.

The input protection uses a 75V GDT (no MOV because the input voltage range is very small) and CPC3902 depletion mode MOSFETs on both inputs. The CPC3902 is rated for 250V and has an RDSon of 2.5 Ohms at zero bias. When IN+ goes above 0.7 V, the FET on IN+ is turned off by a comparator (propagation delay is about 300 ns). When IN+ goes below -0.7 V, the FET on IN- is turned off. The hysteresis on the comparator for undervoltages is kind of weird, but I found in simulation I needed the turn on threshold to be very low to avoid oscillations. I will probably need to add some more inductance to IN+ to limit current for fast rising signals, but I will figure that out as I get into layout.

The power supply uses two buck LT8608S converters to generate 8.5V and 2V rails. The 2V output is fed into a Cuk converter using an LT8365 that is powered with the 8.5V rail to generate -3.4V. The Cuk was somewhat painful to compensate in simulations, but it seems to be reasonably stable. Also, I couldn't find any loosely coupled inductors that seemed suitable, so I just used a normal coupled inductor and added a single inductor to the output. I was having problems with coupling factors above about 0.95 in simulations. There won't be large load spikes on the negative rail, so I don't think the long response time of the compensation network will be too problematic. I had wanted to use a switched cap inverter for this, but I couldn't find any that seemed a really good fit for the application, especially because I didn't want to have to power it with the +5V4 LDO. The power supply is a separate module because I wanted to keep as much power dissipation off the board as possible and I wanted to be able to try something else if this ended up negatively impacting noise. By the way, I left all the oscillators free running rather than trying to sync them to a clock on the board. I am curious about opinions on whether this will be problematic.

[Kleinstein]

I don't think the protection with Q20,Q21 is really optional. It schould be the main way of clamping.  For simplicity I would prefer a BAV199 there  (should also fit on one of the footprints of a MMBF4117).

The input protection with the FETs on different sides is a bit unusual, but it could still work.

I think some of the capacitors (e.g. C119, C1120)  in the ADC drivers are a bit large and would slow it down a bit much.

With the gain at the ADC driver, the input protection via the switches may engage a bit late. So maybe have the option for lifted levels (e.g. 3 more resistors) at U32.

[CurtisSeizert]

Thanks for the comments. You are probably right with the settling time of the ADC driver, and I may reduce the caps to 1.5 nF. It takes about 120 us to settle to 1 ppm with the current values from a full-scale step, which could probably be better. My plan for using CDS for the driver was to have that clocked at 1/2 the speed of the modulator, so it would share that settling time with the input stage settling. From ADIs simulator, it seems like the 68R/2.7nF combo for the ADC input should be settled to <0.1 ppm at 500 kSPS as far as charge kickback goes.

Good idea on popping a few resistors in to shift the levels on U32 in a few tenths of a volt.

My goal with the clamp was to have the bootstrapped BAV199 clamp the voltage at about +/-3V, but that is playing pretty close to the line for the PE4140. A BAV199 in the place of the 4117s would be more robust, so I think you are right about making that switch. I'll keep it as such because I can just sub in a BAV199 for one of the FETs as you mentioned. I realize the FETs on both inputs is somewhat odd, but I realized that with N-channel FETs being driven by the voltages available on the board, there would be no way of turning off a FET on the positive input for a large negative overrange. This wouldn't be an issue with JFETs, but I thought it would be better to have the series current limiters survive until sparkover on GD1 at 75V, and options for 75V JFETs are very limited. I kind of like this more than back to back FETs for a NVM because I can use the symmetry to cancel out thermal EMFs, presuming I can accurately guess the direction of the thermal gradients.

[Kleinstein]

The settling at the ADC driver is not so much the 68 ohm and 2.7 nF, but the presumibly 3 K and 2.7 nF at the x3 gain part.   Anyway changing the values is a thing a think about later.

For testing it could be good to have an option to have an alternate input path to the ADC -  maybe even via U34C.
In the circuit I don't see many test points.

For some of the parts that see higher frequency operation (e.g. U38 as the final ADC drivers and maybe the ADC) it may help to have additional resistance (e.g. 5-10 ohm) or ferrites in the supply paths (before the decoupling caps). This can keep the supply cleaner.

[CurtisSeizert]

Points well taken. I have plenty of room on a 150x100 mm board, so I am adding test points as I go. Note that the gain of the composite diff amp is 2 (Rg = 700R, Rf = 1k4). I like the idea of being able to feed a signal to the ADC directly using the unused section of the TMUX4053. I may also add a footprint for an ADR1399 daughterboard to have the option of a higher quality reference.

I am making pretty good time on layout, but it is not easy. I have moved the components that dissipate the most heat out from the RF shields that I am using as thermal baffles and put in cutouts to isolate the sensitive parts from external thermal gradients as much as possible.

[CurtisSeizert]

A quick status update. I have finished laying out the board(s) for rev B of the NVM and written a decent chunk of the setup code. I attached 3-d renders of the top and bottom of the boards. On the top, the signals start in the upper-lefthand corner and move down and right. The MCU is the LQFP-64 in the lower right corner.  I was glad to have done some of the coding before finalizing the board design, because I realized my original timer scheme was not going to be optimal for what I needed to do. I have attached a quick timing diagram of what an autozero cycle would look like, but it does not include all the outputs. I will beef this diagram up at some point to make it more understandable. There are two synched timers that control the PWM signals for the (de)modulators with the same period, one with double the period for CDS for the ADC, and one with half the period (i.e. synched to the phases of the modulator timers) where the output compare triggers the timer that pulses the CNV pin on the AD4032. To make this easiest, the CNV pin needs to be attached to TIM1 or TIM8 on an STM32 because they have a repetition counter. The timer that triggers the CNV timer allows one to adjust the settling time of the input before starting conversions with the ADC. Also, the modulator and demodulator timers needed to be 32-bit timers to give fine control of the switching deadtime while allowing (essentially) arbitrarily long autozero cycles.

The BUSY pin is connected to an external interrupt pin that triggers a read of the output data shift register of the ADC.  I noted in a previous project that with an STM32F446 at 180 MHz, I could get a time of 160 ns from the falling edge of the BUSY signal to the falling edge of the NCS signal. With the QUADSPI bus clocked at 90 MHz in that case, I could retrieve the data from a previous conversion on four lanes before the next pulse of the CNV pin at 2 MHz with margin for the 19.6 ns quiet zone (Zone 1 transfer, see AD4030-24 datasheet p. 29). At 500 kSPS, that window is ~6x longer, so I should be able to run the MCU at 48 MHz, assuming things scale linearly. I expect it will be a bit better than that because the U5 uses the Cortex M33 instead of the M4. Obviously, none of this is possible with STM's HAL.  I will post all this to Github tonight or tomorrow and share a link to the repository.

While I was laying out the board, I realized that my comparator-driven input protection scheme would not easily be made to work for powered-off input protection, so I changed it to what I think to generally be a better scheme. It is more or less a depletion mode FET current limiter. For the positive input, the gate of Q2 is connected to the source via R79 and Q13 (the latter as a low-leakage diode). With typical specs for the CPC3902, this puts the current limiting at 10 mA. With maximum Vgs_off, it would be ~15 mA. D13 and D12 are low capacitance RF Schottky diodes so that the input is not burdened with the large Ciss of two CPC3902s in parallel. The FBs and dampers (R1 & C1, R81 & C47, and R76 & C48) are there to deal with spikes from fast rising signals coming through the Coss of the FETs. In simulation, this kept the voltage between the nodes K2_IN+ and K2_IN- at <3V even with 100V spikes with a rise time of 1 ns. The maximum current through the FETs allows a constant voltage of 100V over either Q2 or Q1 while remaining safely under their maximum power dissipation of 1.8W. With typical values for Rds_on, the source impedance seen by the input chopper is ~5 Ohms in series with 1 uH. In simulations, the phase margin of the input chopper is about 80 degrees with the equivalent input impedance of this protection block in place.

[Kleinstein]

It is an interesting way to make the protection. Looks like it may work, as long as the input is OP with the voltage needed to turn of the depl. FETs.  The maximul current may well be lower than 10 mA, as there is also quite some voltage drop at the diode / diode used JFET.  It can be a nice version with low series impedance, but it is somewhat limited in the voltage.

[CurtisSeizert]

I am not too concerned about the current limit being less than 10 mA. It is actually not that difficult to change this to work with arbitrary voltages. For positive input protection, for example, you can put a zener in between R78 and K2_IN+ and bootstrap the node between the zener and R78 with some moderate impedance. The gate for Q2 would be connected to this node as well, via R80 and D12. Such a scheme should limit the input voltage to ~V_zener + 2 V with minimal leakage and additional capacitance. You would probably want the bootstrap to rail out around the zener voltage.

By the way, I have created the github repository. Here's the link: https://github.com/curtisseizert/Nanovoltmeter

[CurtisSeizert]

I had to put things on hold a bit while I did some work on my house, including replacing the old knob and tube wiring. My reflow oven had been working on a 15A branch that was wired with ~120 year old 14 gauge Al wire, where neutral was regularly 5-7 VRMS off ground without it on. Also, I had grounded my instruments through the shield of some 75 Ohm coax that plugged into my UPS. It was sketchy.

Anyways, I have assembled two NVM main boards, one using an LTC6655, and one using an ADR1399. By the way, I switched the heater leads in the pinout for the ADR1399 on the schematic (and boards I had made), so I will post a revision on Github. There are a lot of components on this board (about 470 with the ADR1399, somewhat fewer with the LTC6655), and it took quite a while to populate the boards. This is about as complex a board as I would want to hand assemble. Apparently when I was sourcing components, I was too cheap to get enough of the BMF gain setting resistors for two boards, so those are not populated on the assembly I have shown. There is still some more code to write, so it will be a bit longer before I can power it up and test it. Also, I did select the JFE2140s I used in this case, and I was able to get the average Vos down below 15 uV in both cases, so I may be able to reduce the gain on the Vos correction loop more, but I will try it out before I made that modification.

I also made a separate board where I just populated the input protection circuitry to be able to abuse it, so we will see how that works.

[CurtisSeizert]

A quick status update: I haven't finished writing code that works quite yet. As I may have previously mentioned, I am not using STM's HAL and am going for direct register-level coding here because I found in some previous work that there was too much overhead in STM's drivers to meet strict timing requirements for completing transfers from the AD4030-24 on the QSPI bus at 2 MSPS. That was done with an STM32F446 (Cortex M4), and this uses an STM32U575 (Cortex M33), and there are some differences in how things are set up. Hopefully I can get something working over the weekend.

The PSU daughterboard positive rails work well, but it will require a revision for the Cuk. I like the LT8608S buck converters for efficiency and noise. The 8.5V output is about 83% efficient at 26 mA current draw, which is the minimum required to get it from burst mode to pulse skipping mode. Noise on that rail is a few mV p-p out to 100 MHz. If I float the SYNC pin, it should stay in pulse skipping mode, which is less noisy. I still need to test the efficiency of the 2V output, since it draws a lot more current; it feeds both the 2V rail and the Cuk converter that is used to make the -3V3 rail (in order to keep the duty cycle for the Cuk in a reasonable range). A revision is required to correct the pinout for the coupled inductor in the Cuk and have everything fit under the shield. I tested it with a couple transformers I wound for the purpose, but I'd like everything to be clean to keep radiated emissions to a minimum. I also added some snubbers to the switching nodes of the buck converters in the revision because they are operating in DCM, though the output noise is good without them.

Both the ADR1399 and LTC6655 versions of the board power up successfully now, but I had to fix some schematic issues with the ADR1399 block. I have attached the corrected schematic. As drawn, it will not be able to maintain current regulation at very low dropout conditions for ADR1399 voltages near the upper end of the range, so that will be something to consider for a future revision of the main board. With an MMBF108, R154 = 25R, and R70=3.3M, this should keep the reference current >3 mA for the whole range of possible reference voltages, with a minimum dropout voltage of 0.2V. It may also be preferable to omit C156 for better PSRR. I haven't seen this sort of topology used in this application, but perhaps there are instances I am not aware of. The block surrounding U42B is just for ground current cancellation.

The input protection circuitry works well for slowly rising overvoltages applied to the inputs, which I have tested up to 60V. However, it seems to ring with quickly rising voltages, so the input chopper would be subjected to +/-10V for about 20 ns if one plugged in 60V, at least with the current values for resistors, capacitors, and ferrites. The voltage was clamped at 2.3-2.4 V for each rail, and the current when the voltage exceeds this was 6.5-7 mA (it is slightly different for each rail).  If I short the inputs after the protection circuitry, the DC resistance is about 4.4R. The capacitance of the input section is 210 pF at 1 kHz (with 0.2V excitation), which is only 30 pF more than the total value of the snubbers. Of course, there is a fair bit more capacitance from Cgs of the depletion mode FETs, but that is in series with 1M. I am going to keep playing around to see if I can improve the performance with quickly rising overvoltages with some different component values, but I am happy with what I have seen outside of that.

[miro123]

Thanks for the update.
There are a lot of innovation going on your project. From analogue technique to power eletronics and then the digital bleeding edge technologies.  Are you using STM32U5  DMA Low-power background autonomous mode? Are you using STM32U585 SMPS or just use external dc-dc- cuk's
Send me a PM if you need help with STM U585 setting

[Andreas]

Hello,

where comes the heater supply from?
with 10V (+7.5 / -2.5) you are in a area where the PSRR is worse than 1 ppm/V.
Ideal would be something around 25-26 V for the heater.

https://www.eevblog.com/forum/metrology/adr1399-reference/msg4503037/#msg4503037

with best regards

Andreas

[Kleinstein]

The low side of the ADR1399 reference looks a bit odd. There is the rather low resistor to "measure" the current, but essentially all of the current would still come via the transistor.
I have not seen this part in the initial circuit and it is now likely too late for a larger change.  A more logical solulution here might have been to have the 7 V reference split as +5 V and -2 V. So that the high side could directly be at the 5 V ref. out level and the -2 V level could be controlled be the "gain" stage to get -2/5 of the high side. So with no direct ground link for the refrence. One would get a little more headroom to control the current from an auxiliary level of some +7 V.

For the protection against fast transients some series inductance could help. It would still let some current through, but the current is at least reduced and as a side effect one gets some EMI filtering.

[CurtisSeizert]

Thanks for the update.
There are a lot of innovation going on your project. From analogue technique to power eletronics and then the digital bleeding edge technologies.  Are you using STM32U5  DMA Low-power background autonomous mode? Are you using STM32U585 SMPS or just use external dc-dc- cuk's
Send me a PM if you need help with STM U585 setting

Thank you. I may need to take you up on that. I actually mislabeled the schematic and am using the STM32U575RIT (not Q), which just uses an LDO for the core voltage. Simply using a low power MCU at a low voltage helps a lot with power consumption (and, importantly, fed with a buck regulator). Once I get some minimal code going, I may work on implementing some of the fancier low power modes. I have attached the revised schematic for the PSU daughterboard. The 2V0 rail feeds TPS7A20s to make the two 1V8 rails. The Cuk is only for the negative rail as I have found they are often difficult to compensate at very low current draw.

I am going through the debugging process to make sure the various peripherals are up and running on a separate board with just the MCU and associated components. I am really still in the stages of learning as I go with coding some of this stuff, and the way it is currently set up is fairly basic with a handful of interrupts and GPDMA for the octospi bus that receives data from the AD4032. I am not aware of any good bare metal code examples for this series that goes beyond blinking a LED, which I can handle fine on my own. Right now I have all the timers working as planned, which was the most complex part of planning out the code so far. There are separate 32 bit GP timers for the modulator, the demodulator, the ADC CDS routine, and the settling delay between switching phases before beginning ADC conversions. The CNV pin is pulsed in one shot mode using one of the advanced timers (TIM8) for the repetition counter, and the falling edge of the BUSY signal on EXTI0 triggers the data read. With all the peripherals running and SYSCLK at 48 MHz, the oscillators and MCU pull about 10 mA, so that is 20 mW, which I don't think will be a big problem as it is a small portion of the overall power consumption.

I am interested to see if the response time to an external interrupt is better for the M33 than it is for the M4. With the F446 at 180 MHz, the best I could do was 160 ns between the falling edge of BUSY from the ADC and the falling edge of NCS from the MCU, though in that case I did not have hardware control of NCS, so it took a couple cycles to write the appropriate GPIO register. There is probably a better way to do this, but triggering ADC data reads with the falling edge of BUSY is probably the easiest way to code it. At 2MSPS with the Q- or OSCTOSPI clock at 90 MHz and 4 lanes, you need to be at or below 100 ns to get within the available window of 198 ns with a bit of margin. At 500 kSPS, I have a much more leisurely 1.2 us, so this naive way of structuring the transfer will probably work.

Hello,

where comes the heater supply from?
with 10V (+7.5 / -2.5) you are in a area where the PSRR is worse than 1 ppm/V.
Ideal would be something around 25-26 V for the heater.

https://www.eevblog.com/forum/metrology/adr1399-reference/msg4503037/#msg4503037

with best regards

Andreas

I was not aware of that rather poor heater PSRR. As I currently have it, the heater gets the battery voltage for the positive supply and the Cuk output (-3V3) for the negative. In theory that would be 20V at full charge to about 15V with the cell voltages at their cutoff of 2.9V. Obviously, if that 1 ppm/V is a general phenomenon, this would be a big issue, but I could address it with another converter on the power supply at the expense of no longer being able to monitor the battery voltage with the MCU ADC. I don't mind this too much since I will already be doing a revision of the PSU. I will check the PSRR with my setup and report back. Thank you for bringing this effect to my attention.

The low side of the ADR1399 reference looks a bit odd. There is the rather low resistor to "measure" the current, but essentially all of the current would still come via the transistor.
I have not seen this part in the initial circuit and it is now likely too late for a larger change.  A more logical solulution here might have been to have the 7 V reference split as +5 V and -2 V. So that the high side could directly be at the 5 V ref. out level and the -2 V level could be controlled be the "gain" stage to get -2/5 of the high side. So with no direct ground link for the refrence. One would get a little more headroom to control the current from an auxiliary level of some +7 V.

For the protection against fast transients some series inductance could help. It would still let some current through, but the current is at least reduced and as a side effect one gets some EMI filtering.

Yeah, that probably would have been better. I have quite a bit of experience using that ground current cancellation technique in ADR1000 and LTZ1000-based reference modules for ensuring that the low sense voltage remains near power ground with potentially variable contact resistance on the header, and it works well for that purpose. With the OPA2205A, things usually settle out to a few tens of uA ground current. It is nice to have a low current sense resistor because it changes the cutoff frequency for op amp noise. With the values here it is only about 4 Hz. So it may not be ideal, but it does work, and you have to admit that the current source for the Zener is pretty cute.

I agree some series inductance would help. With all the beads in series, I think it should be around 2.4 uH right now, which is not much. I am wary of adding too much given my experiences with degrading the phase margin of composite amps with a large input capacitance, especially since the autozeroing with this is predicated on the discrete portion operating at very high gain (from simulations, it is about 70 dB), which means the loop gain is quite high even with a large divider in the feedback network. That said, I can experiment pretty easily by just adding ferrite beads to the input leads or adding turns to said ferrite beads. I was thinking about trying out Toshiba's Amobeads for this purpose along with more traditional cable ferrites.

[miro123]

I am going through the debugging process to make sure the various peripherals are up and running on a separate board with just the MCU and associated components. I am really still in the stages of learning as I go with coding some of this stuff, and the way it is currently set up is fairly basic with a handful of interrupts and GPDMA for the octospi bus that receives data from the AD4032. I am not aware of any good bare metal code examples for this series that goes beyond blinking a LED, which I can handle fine on my own. Right now I have all the timers working as planned, which was the most complex part of planning out the code so far. There are separate 32 bit GP timers for the modulator, the demodulator, the ADC CDS routine, and the settling delay between switching phases before beginning ADC conversions. The CNV pin is pulsed in one shot mode using one of the advanced timers (TIM8) for the repetition counter, and the falling edge of the BUSY signal on EXTI0 triggers the data read. With all the peripherals running and SYSCLK at 48 MHz, the oscillators and MCU pull about 10 mA, so that is 20 mW, which I don't think will be a big problem as it is a small portion of the overall power consumption.

I am interested to see if the response time to an external interrupt is better for the M33 than it is for the M4. With the F446 at 180 MHz, the best I could do was 160 ns between the falling edge of BUSY from the ADC and the falling edge of NCS from the MCU, though in that case I did not have hardware control of NCS, so it took a couple cycles to write the appropriate GPIO register. There is probably a better way to do this, but triggering ADC data reads with the falling edge of BUSY is probably the easiest way to code it. At 2MSPS with the Q- or OSCTOSPI clock at 90 MHz and 4 lanes, you need to be at or below 100 ns to get within the available window of 198 ns with a bit of margin. At 500 kSPS, I have a much more leisurely 1.2 us, so this naive way of structuring the transfer will probably work.

Few thinks comes in mind.
1. You can use the nucleo board for software debug and prototyping. HW design of those boards not good but they are perfcest for sw validation. https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
2. Honestly I did not follow completly your design and requirements but few this pop up in my mind.
    - using GPIO for time critical application is not the good way. Modern processors has many busses and bridges between. This allows nodes with different speed to communicate efficiently. The GPIO periphery is ot directly connected to CPU core as it was in old days - 8051/PIC and AVRs. Just for test try to togle one pin in one endless loop. You will see that frequency does not strongly depend on CPU core sped. More from global picture mostly from all bus speeds
   - The main STM32 advatage is the periphery and interconnection between them. In general - all what we do in FPGA can be done with programming of periphery. Unfortunately the kerning curve is quite steep. Most variant have 2000+ pages URM pdf. + datasheet 100..200pages + App notes.


My advice is to use time compare-capture capability - reaction time there is in nsec range -
Interconnection between periphery happen via triggers and  events. - I suspect your application requires
solution 1 - SPI ISR
 - Timer CCR output start external ADC - ADC toggle STM Interrup Input - ISR hanle data
solution 2 - Poll spi for data
precondition - init spi + spi FIFO
 - Timer CCR output generated start pulses using the same setting as solution1 - timer period is set to 2usec. - 500KHz
 - Main loop pools for SPI data
Soluti0on 3 - Use DMA - the one that I preffer . Disadvantage requires deep dive in STM documentation or you can ask me to write some demo code using STM Cube and HAL

 -
500Ksps - seem easy task. I have been running 100MHz QSPI to execute code from external SPI flash But EMC /radiated/ was terrible. Does ADC support LVDS outs?

[CurtisSeizert]

It is difficult to fully explain what needs to happen in the code here, but the software NCS for QSPI was on an old project where I realized I needed to change pins. Anyways, nothing time critical on GPIOs here, and there are a lot of synchronized timers. Basically, the ADC is oversampling, so I am not even clocking out 500 kSPS as it does internal decimation. I am using OSRs in the range of 64 to 1024. With the 1.2 us window I have, I am almost certainly going to use the falling edge of BUSY from the ADC (connected to EXTI0) to trigger the read. Right now I use an ISR to do a blocking transfer over OCTOSPI using hardware NCS. It would be nice if I could trigger OCTOSPI to read the ADC data directly with EXTI0, but I haven't figured out how to do that yet. Because of the OSR, I actually cannot use a CC on TIM8, which handles timing for the conversion cycle, without checking the state of the BUSY signal.

I do actually have things up and running to some degree now. The MCU DAC and the AD5686 are working and providing the switching levels. There was an oscillation due to Q19 sourcing more current on the Vcm node than the op amp driving it could sink, but I was able to take care of that by bending up the leads for the collectors and soldering in 10k resistors to Vcc. It is not performing as expected yet, but I will keep troubleshooting. It looks like the current draw at 500 kSPS (with the LTC6655) will be about 32 mA on the 8V5 rail (about the same on -3V3) and 18 mA on the 2V0 rail, but this could come down a bit when the loop is actually regulated.

[miro123]

See attached example for initialization of IO as interrupt pins. Code was part of exeisiting project for STM32H7 but periphery should be the same for U5xx

[CurtisSeizert]

See attached example for initialization of IO as interrupt pins. Code was part of exeisiting project for STM32H7 but periphery should be the same for U5xx

Do you have a sense for how many clock cycles it took from the trigger on the EXTI pin to get into the ISR? I am using a board that I populated with just the MCU and associated components. I connected the timer for the CNV pin to EXTI0, and with a very minimal ISR, it is around 34 clock cycles from the falling edge of the trigger to the falling edge of NCS. It is only five lines of assembly code to do the write to the OCTOSPI IR to trigger the indirect read. I haven't used a profiler or anything to see how many lines it is to get to the ISR, but I imagine that is where the bulk of the time must be coming from. It is not really an issue for 500 kSPS, as falling edge of BUSY to rising edge of NCS is 974 ns at 48 MHz (using 4 lanes and prescaler of 1 on OCTOSPI), and I have 1.7 us to complete the transaction. Perhaps global interrupts are just not that fast and it would be better to handle things through GPDMA. For now that is not a concern, but it is something I am curious about. The code related to the ISR is below.

Code: [Select]


void nvicInit(void)
{
// Set Interrupt Priority
NVIC_SetPriority(EXTI0_IRQn, 0);
NVIC_SetPriority(GPDMA1_Channel1_IRQn, 1);
NVIC_SetPriority(TIM2_IRQn, 2);
NVIC_SetPriority(TIM7_IRQn, 3);

// Enable interrupts
/* EXTI0_IRQn is enabled separately after AD4032 has been set up */
NVIC_EnableIRQ(GPDMA1_Channel1_IRQn);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_EnableIRQ(TIM7_IRQn);

}

void EXTI0_IRQHandler(void)
{

OCTOSPIRead();

EXTI->FPR1 |= (1UL << 0);

}

uint32_t OCTOSPIRead(void)
{
OCTOSPI1->IR = 0U; // Trigger read by writing to OCTOSPI_IR

while(OCTOSPI1->SR & OCTOSPI_SR_BUSY); // Wait for operation to complete

OCTOSPI1->FCR |= OCTOSPI_FCR_CTCF;
return (uint32_t) OCTOSPI1->DR; // Read from FIFO
}

Also, I had assumed that the peripherals would be essentially the same between the F446 and the U575, but there are actually a number of subtle differences that make things tedious to sort through. The SPI FIFO is completely different, as is the way that OCTOSPI handles addresses, instructions, etc. The DMA is completely redone, but that's not a peripheral. More annoyingly, they have moved bitfields between various registers within these peripherals but have not done anything about the terrible non-contiguous bitfields that are apparently kept for compatibility in other peripherals. Maybe I'm in the minority here, but if you're going to break compatibility on nearly every peripheral, just get rid of the goddamn non-contiguous bitfields too.

Edit: Fixed a mistake in the conditional in OCTOSPIRead()

[CurtisSeizert]

I have given up on using octospi for the ADC reads, but thankfully I have SPI1 connected for reading and writing device registers on the AD4032, so I can use that for one-lane transfers of data, and I can stream output data over UART.

In the analog domain, things are getting there, but there is a large, persistent offset voltage on the output of the chopper block that is unrelated to the phase of the modulator/demodulator (about 0.8V on the 101x gain setting). My hypothesis is that it came from gate breakdown of one of the demodulator PE4140s when I was getting large swings on the Vcm node, leading to non-negligible gate leakage. It feels like things are getting close, so hopefully I can get some decent data out of this thing soon.

[CurtisSeizert]

It works! I had to make some modifications to the front end to make it essentially the same as it was in the first iteration to make it stable. I believe the persistent offset was from the load resistors being too small, but I changed them on a hunch and haven't had a chance to think of why it worked. The main issue in the oscillation was the dual emitter follower after the folded cascode. That was in place to better isolate the switching spikes from the demodulator switch, but I figured the capacitance in that switch is so small that it probably did not help much to have it in series with the base-emitter capacitance of the MBT6429. All of this work has used the LTC6655 version.

The ADC data make sense, but I still have some work to do to null out the ADC and associated signal conditioning offsets from that. Both the gain settings give very low residual offsets of 70 and 100 nV for low and high gain, respectively, with an arbitrarily chosen 250 Hz modulator frequency. I have set the offset DAC by hand with the debugger connected, and I have gotten it as low as I can with the scope. Closing the control loop in software at this point should not be too bad. Ultimately, I want to algorithmically set the switching levels for the modulator and demodulator to minimize injected charge, but that will be more difficult (and time consuming) to code.

With the default levels I chose, the switching spikes are much better than they were in the proof-of-concept version. I attached a trace at 1000x gain from the front end scaled to be RTI. The scope is AC coupled because the waveform is centered around 2.5V (RTO), and I used 50 averages because the scope is quite noisy at this level. At the op amp output, the previous version had switching spike peaks around 900 mV; these are less than 9 mV RTO. This is actually probably an overestimate because I am triggering on the spikes here, thus selecting the ones that are larger than the threshold. Changing polarity in the opposite direction actually gives much smaller spikes regardless, and dialing in the correction loop also helps.

I will continue testing once I get the code straightened out for automatic regulation of the Vos correction DAC and look at NSD, bias current, etc.

[Kleinstein]

The emitter followers at the input stage would add up to a factor of 5 to the front end gain. Without the emitter follower the transconductane gain is directly from the input stage. With the emitter follwer on should get a voltage gain with the 47 K to ground and then 2x5 K around the switch to convert back to a current.
So one would get a correspondingly higher speed or need larger compensation capacitors to get back to the old speed. This may explain a tendency to oscillate.

The switching spike is surprisigly short. So not much time lost for settling around the spike.
The ADC may already have some difficulty to resolve the spike, at least in real time.

For the scope picture the modulator clock should be a good trigger, to avoid trigering on a noisy signal, which may cause artifacts with averaging on the scope.

There is no absolute need to get exactly the same voltage for both phases. Even if there is a residual difference the average would still be a good way to get the result, at least for the slower sampling rates.  One has the freedom to accept some residual AC, if this helps reducing the switching spike at the input. It should help with the symmetry.
The critical spike / point to adjust would be at the input, not the spike at the OP-amp / output.

For the start I would use a manual adjustment to see how the gate voltages effect the spikes (could be different for both directions).
Only than could one think about an automated trim. This may need some extra hardware so that the µC can see the input spike, so not just coding.
I am not so sure that the output spike really correlates with the input spike.

[CurtisSeizert]

The emitter followers at the input stage would add up to a factor of 5 to the front end gain. Without the emitter follower the transconductane gain is directly from the input stage. With the emitter follwer on should get a voltage gain with the 47 K to ground and then 2x5 K around the switch to convert back to a current.
So one would get a correspondingly higher speed or need larger compensation capacitors to get back to the old speed. This may explain a tendency to oscillate.

The switching spike is surprisigly short. So not much time lost for settling around the spike.
The ADC may already have some difficulty to resolve the spike, at least in real time.

For the scope picture the modulator clock should be a good trigger, to avoid trigering on a noisy signal, which may cause artifacts with averaging on the scope.

There is no absolute need to get exactly the same voltage for both phases. Even if there is a residual difference the average would still be a good way to get the result, at least for the slower sampling rates.  One has the freedom to accept some residual AC, if this helps reducing the switching spike at the input. It should help with the symmetry.
The critical spike / point to adjust would be at the input, not the spike at the OP-amp / output.

For the start I would use a manual adjustment to see how the gate voltages effect the spikes (could be different for both directions).
Only than could one think about an automated trim. This may need some extra hardware so that the µC can see the input spike, so not just coding.
I am not so sure that the output spike really correlates with the input spike.

The emitter followers I deleted (Q19 in the attached) don't provide any additional voltage gain prior to the op amp. The point of the resistors around the switch was to increase the impedance at the inverting input to slow down the op amp integrator. They are symmetrically placed about the switch so that source and drain see approximately equal impedances. When I was simulating this input stage, increasing the value of those resistors did not increase the loop gain, but it did alter the frequency response. They may speed things up, but they are operating at a a rather low collector current, so they also introduce some delay. I calculated this while I was selecting values, but I don't have the results handy.

I actually have triggered on the demodulator clock, but doing so shifted the levels of the switching cycle as observed on the scope somewhat. I may try to use both outputs and subtract them to see if that helps things. It appears to be helpful to keep the transitions as small as possible for minimizing switching spikes from playing around with this some more. My control loop seems to have a tendency to work well and then go crazy. I think this may be due to something going awry with the DAC SPI bus. The problem seems to disappear when I put a breakpoint around where the update DAC code is, so I haven't figured out what the issue is yet.

The ADC input circuitry will slow down the spike somewhat, though I don't know exactly how much it will delay it by. The auto adjustment was actually for overall bias current by switching in a 10k resistor between the inputs with a relay that is available on the board. I can adjust the levels to try to match the voltages with and without the resistor switched in. I will need to see if the results of such a thing actually correlate with reduced input bias current well, but I am not quite there yet. I have done some experiments on a board I made to experiment on just switching levels with the PE4140, but I'll have to see if those lessons hold for this more complex system.

[Kleinstein]

If removing the emitter follower work well, this is good. The added dealy from slow. low current transistors can indeed be an added problem.

The scope probe could be enough loading to effect the timing of the chopper signal a little.

The 10 K resistors may be a bit low to measure the bias current, but it could be enough to compare the response right after switching. The larger input current spike, the larger effect of the 10 K resistor at the input on the switching spike seen at the output. If going by the bias, one could increase the chopper frequency for the adjustment as the bias current from switching should scale with the frequency.

For the adjustment of the spikes there may also be the option to use a little delay between the chopper side and the demodulator side. The demodulator side may also have a short neutral phase. So it is not just the gate voltages, but also some timing to play with.

A SW problem that disappears with a breakpoint can be hard to track - maybe be a timming issue / race condition.

[CurtisSeizert]

OK, at this point, I think it is fair to say that I have it in a reasonable state where the core feature works. The issue I was having with inconsistent SPI writes to the offset DAC was due to a number of things going wrong, actually. I made the way the data are indexed more robust so that it resynchronizes to the timers that drive the modulator, etc., every cycle. I am trying to get DMA to work on this thing so I can offload the UART transfers, which take a fair bit of processor time waiting for various flags to be set when it's run in a blocking configuration, but I accepted doing blocking transfers for the moment to get a feel for how the meter is working.

The way that data are gathered is reasonably simple, at least at a high level. The ADC input switches operate at half the frequency of the modulator/demodulator. When the modulator changes phase, the meter waits for a settling time to elapse (I have used 10 us as a default) and then begins triggering conversions using the onboard sample averaging of the AD4030-24 (I ended up using the 2 MSPS-capable part). The ADC data are used to populate an array for each mod cycle, and average offset is calculated by subtracting the elements of the second half of this array from those of the first half. If the ADC input switches are in the inverted configuration, the average and average offset are negated. This is done for some whole number of ADC input switch cycles, and if the offset is positive, the offset DAC code is incremented. If it's negative, it's decremented. This actually seems to make the average offset stay considerably below the calculated LSB size of 43 nV, even when the update is done much more slowly than the time constant of the RC filter on the DAC amp. It settles out quickly enough this way that there's no need for anything fancier, though I have programmed in a known value that's pretty close as the default.

I will probably need to do a bit more work on sample processing. As one can see from the NSD of some data taken at 7.5 SPS using 1000x gain, there are spikes at f/(2^n) where f is one of the clock frequencies. They are all harmonically related, so I don't know which. These may be related to insufficient settling time (remember, the ADC signal conditioning is much slower than the front end amplifier). I suspect the ADC switching is the likeliest culprit because it is slower and probably spikier. I will continue investigating on that front. Even with this, the noise at 101x gain is remarkably good, and it is looking like a dynamic range of >140 dB is doable.

I attached some sample data showing settling of the meter from reset at 101x gain and the NSD to 0.01 Hz at 1001x gain. Both were 7.5 SPS with a modulator frequency of 30 Hz. Also, I have noticed that the modulator frequency has a noticeable but relatively minor impact on offset voltage. On 1001x gain, I see about 75 nV offset at 30 Hz and about 105 nV at 990 Hz.

[Kleinstein]

There is still something odd going one, with a period of some 8 seconds on so.  The 30 Hz modulation may cause interference with 60 Hz mains, though ideally it should still suppress mains hum well.

Some 8 seconds could also be the speed of thermal oscillations - at least I have found some such oscillations in that frequency range with a closed case. The protection part is still befor the chopper part and could react to themperature changes. It could make a difference if the short is internal via the relay or external, including the protection.

Except for the extra low frequency the noise spectrum looks really good.
As a baseline it could also be interesting to look at the noise of the amplifier without chopping. This could give a hint on where the 1/f starts to become significant and when faster chopping would not help much anymore. Chances are one could get away without polarity reversals at the ADC for this.

[CurtisSeizert]

I looked at the spectrum again, and I realized it's not what I originally said - the spikes are harmonics of about 0.12 Hz. I think it is plausible that it's aliasing from the line frequency, but I'll see what I can figure out. The very low frequency noise is a bit odd; I have the output attached to my 3458 and it is very quiet at 100 NPLC, even with thermal EMFs from the SMB connectors. I am not powering it with a battery but rather with a bench supply feeding 15V to the SMPS daughterboard, so it's possible that ground loops with the debugger attached are to blame. I'll test these things and report back. From simulation, the NSD should be around 1.1 nV/rt Hz. The ADC and associated drivers will not add much to that because of the first stage gain.

[CurtisSeizert]

I've done a handful of experiments on the NSD, and I have noticed a few things about the spikes:

-The fundamental is always f_mod/64
-Changing modulation frequency has no impact on the frequency ratio
-Changing the number of cycles per DAC update has no impact
-Changing the gain has less than a 10x change on the size of the fundamental, but it does change the lp filtering characteristic for the peaks (see the attached spectra to see what I mean)
-Turning off the ADC input switching has no impact
-Adjusting switching levels and dead times for the modulator and demodulator has minimal impact (but is helpful to optimize nonetheless)
-The spikes are also present in the offset data, but I have not compared the phase between offset and average

I feel like the spikes represent an idle tone of some sort, but that is strictly at hunch level. As the fundamental is 1/64 * modulator frequency, a repeating sequence using every combination available for six bits would generate such a spectrum. I haven't done the math on which bits those would be based on the power contained in the spikes, but that's where I am at with it. I don't think it represents a problem per se because those spikes can be filtered by averaging. I am curious to see whether the spikes are present in the analog output of the chopper stage.

I have also been checking the overrange flags from the AD4030, and there are some clear patterns, but the reasons for some of these issues are unclear. For example, the amount of settling time required to avoid an overrange flag is very large considering we're looking at like 100 uV at the input to the ADC signal conditioning block with a range of about -2.3 to 2.3 V. At 315 Hz modulator frequency, I would get sporadic OR flags at 100 us settling time but none at 105 us. There is also some frequency dependence, with 100 us settling at 165 Hz giving OR flags for maybe 10-15% of data points. Some of the datapoints with OR flags are clear outliers, maybe 30 nV from the mean, others are right in line with everything else. I am guessing these are an issue with the code, but I haven't gotten around to putting a probe on the ADC inputs to confirm this.

I do have some pretty good data from an overnight capture I took after optimizing the deadtimes and at least partly optimizing the switching levels. Ultimately, I will probably need to do a design of experiments to optimize these parameters once things are farther along. The capture was taken without the board in a proper enclosure as one panel was missing and a couple polyester cleanroom wipes were stuffed in the opening. The NSD is flat down to just below 0.1 Hz, with some increase in noise density at very low frequencies. I am pretty confident this increase is due to thermal fluctuation. In the time domain, when average the data down to give 1 sample per 10 seconds, I get 5.6 nV p-p over a 20k second interval. I can't get it to be this quiet during the day, so the fluctuations that are present on a long time scale are probably thermal drift of some description. I imagine a proper enclosure would help. Also, these data have only been processed by averaging; the residual offset is really only about 50-something nV. It looks like the sensitivity to temperature variation is better with this revision, but I would need a head-to-head comparison to really determine this. I will also have to bring up the multiple TMP117s on the board to correlate offset to temperature.

[Kleinstein]

In the time domain data from the earlier post is looks like there are some outliers every 8 seconds or so. To gether with a fixed ratio to the modulation this looks really like a software or maybe communication issue (e.g. DMA buffer warp around if a circular buffer is used).  External interference should not give a fixed ratio to the modulation frequency. I would also not absolutely exclude an isssue with the ADC - it is a relatively new chips.

Getting the OR flag is indeed strange - maybe the comparator based external protection is somehow triggert sometimes and this way adding an extra spike in the ADC buffer part. As far as I anderstand it the ADC already does averaging inside the chip to reduce the data rate - so short spikes or fast ringing that causes an overflow my not be visible after averaging. There may also be an issue with waiting and restarting the conversions, e.g. with a buffer not fully empty. It may be worth to also look at the more raw data, as there is a chance that the extra peaks in the frequency domain are a result from a small number of very wrong readings in the time domain, right at the same time in the cycle. The strong harmincs also point in this direction. If it is the first reading after the wait, maybe include a dummy reading instead of waiting.

edit:
It may also be worth to try it without the DAC updates, so a fixed offset setting. The DAC updates could cause extra settling.

[CurtisSeizert]

I am having fun trying to get to the bottom of this. So, the obvious question to ask is do we see those peaks in the analog output. I took a capture at 1 kSPS, got the FFT (attached, referring to the log x axis one), and I immediately thought, no it's not present in the analog output. But then I checked out the modulator peak, and there it is - it just hasn't been aliased as it has in the ADC data. At this point, however, we have people coming over, and I risk the wrath of my fiance if I'm not ready. So, for anyone playing along from home, here are the data. My immediate suspicion is I accidentally enabled dithering on one of the PWM signals, but I don't have time to dig into that.

[CurtisSeizert]

First off, when I suppressed DAC updates after the loop had settled, there were no spikes in the analog out. I know the DAC updates were staying in sync with the modulator, so I worked off the hypothesis that the spikes were probably a phase modulation spectrum of the modulator frequency. I think the broad humps off to the side represent a amplitude modulation from the random chance that the DAC code will increment or decrement, but I may be wrong.

I looked into it, and there were actually a few problems with the code. The OR flag issue was probably caused because the SPI bus could not complete the read within the allotted 1.7 us window, which I think was a function of how busy the CPU was when the interrupt was generated. I didn't check on the actual board and fixed all the timing issues (there were more) on my MCU-only board where the CNV signal is tied to the BUSY line. I had to use some sketchy code to do this, as I am not sure there is a way of using DMA to trigger the SPI bus when NCS is controlled by GPIO. The SPI start signal actually comes before the register write to pull NCS low because it takes a very consistent (but long) time to actually start pulsing SCK after giving this signal. I had to increase the overall processor speed to 64 MHz to do this, but this had no noticeable impact on current draw of the SMPS board (50 mA before and after, much of which is because my stopgap Cuk coupled inductor is probably saturated).

On top of this, the CNV pin was going high during initialization of TIM8, which controls it, so all the blocks were out of phase by one sample. The DAC updates were being performed in a callback function after some unrelated flow control, so there was a variable amount of time from a phase change to a DAC update, which was part of the issue causing the spikes. I ended up putting the update in an ISR that triggers every modulator cycle, so the DAC code actually changes one cycle after it is calculated. This was not enough, and it actually made things somewhat worse because it put the spikes closer to the fundamental and thus at lower frequency in the ADC readings (by a factor of 2). I figured this was probably because the blocking UART transfers were making it take a variable number of cycles to get to the ISR, so I had to figure out why the DMA was not working for that. For the STM32U5, the UART has an 8-byte FIFO, which I had enabled. There is no mention in the reference manual (that I could find) that this will make it not work with DMA, but that seems to be the case. Once I had solved this, the spikes were gone.

With proper phasing of the ADC reads, there is remarkably little energy in the fundamental in the analog out, but there are two broad side lobes. Looking at the ADC data, there are no spikes and the spectrum is essentially flat. The white noise density is closer to the analog out than before, but still a bit higher. If you look at a spectrum of the offset data, you see the lobes, and the white noise density is a factor of sqrt(2) higher. Fixing this stuff did not affect the very low frequency noise, which is still probably dominated by thermal fluctuations. I hope to bring up the TMP117s today to be able to correlate these data with temperature.

[Kleinstein]

The data look really good now.
The side lobes seen at around some 295 and 335 Hz seem to correspond to the position of the noise peak in the offset noise spectrum around 20 Hz. It is still a bit odd where the 20 Hz (or a little more) come from. The difference from the chopper and mains harmonics would be more like 15 Hz.
It is nice that there is not that much extra noise or interference at around the modulation. So there is no limitation to frequencies well below the chopper frequency as with a classical chopper.

I also suspect thermal fluctuations as the main source for the extra low frequency noise. It could make quite some difference between the internal short via K1 and an external short that includes the protection and the terminals.

[CurtisSeizert]

I realized there is an issue with how the correction DAC feedback works, and this is the cause of the humps in the offset spectrum (and sidebands in the analog out). The LSB size for the correction DAC equates to about a 40 nV change in offset (this uses 22k degeneration resistors and a 93 uA tail current for the correction diff pair). The feedback was structured such that if the offset voltage was >0, the DAC code would increment, and it would decrement if it were less than or equal to zero. The problem here is not hard to see - if the offset voltage is, say, 10 nV, incrementing the DAC should bring it to around -30 nV the next cycle, increasing the absolute value of the offset. Next cycle it jumps back positive, making an improvement. So when the loop settles, just under 50% of the DAC updates increase the absolute magnitude of the offset voltage. The broad peak is a resonance in the network, and I believe it should always be centered on a value corresponding to an integer divisor in f_update/n. Here, f_update is 157.5 Hz, and the peak is centered around 22.5 Hz. If you actually change the code to increment or decrement the DAC value by four codes, Q increases, and the center frequency increases to 26.25 Hz (157.5/6). Interesting stuff.

I added a deadband where the code is neither incremented nor decremented to improve the situation. There is still oscillation with a 1 LSB deadband centered on 0. Increasing the deadband to about 2 LSB makes it no longer oscillate, with the offset spectrum presumably looking just like the NSD of the front end were it not modulated. Of the two, this gives less total power in the offset spectrum (up to 55 Hz to avoid the mains frequency). This makes sense, as the direction of the next transition should be random if the code change puts the offset at (theoretically) 0 nV. With the 1 LSB deadband, a code change is more likely to result in an opposite code change next. You can see from the analog out that the fundamental is still pretty tame, and the total noise power related to the fundamental (including the side bands) is lower here by about a factor of 4 (subtracting out broadband noise). The amplitude of the fundamental here is about 5 nVRMS integrating from 312 to 318 Hz and subtracting out white noise.

[CurtisSeizert]

With the temp sensors running, I put everything in an actual enclosure (kind of - there were wires going out to the DC power supply) to get some data on offset voltage measuring the internal short. The modulator frequency was the standard 315 Hz that I have been using, with 104 us settling time and the ADC running at 520 kSPS. The DAC update deadband was +/- 40 nV. Unfortunately, once I put it in the case, the sporadic issue I was having with the temperature sensor near the input stage popped up again, but there are two other sensors, and I just used the sensor near where the ADR1399 is in these plots. Without the voltage reference there, this sensor gives a pretty good idea of the ambient temperature in the case. The sensor near the ADC, which is under a metal shielding cover, reads consistently 0.95 C higher. I also took a capture starting the moment I turned it on to show the warm-up time. There is an excursion in the very beginning of that capture where I turned it off and on again when I realized the input stage temperature sensor was giving bad data in hopes that would fix it. All the captures are averaged down to 0.1 SPS.

The stability of the offset for long-term captures is about an order of magnitude better than the proof-of-concept version, which was sensitive to changing temperatures (i.e., the offset was correlated to the first derivative of temperature). In the enclosure, the residual offset is about 20x better than it was for the internal short on the proof-of-concept version. With the LTC6655 reference, the output is stable within about 1 nV in 15 minutes, 20 if you're being careful. The "corner frequency" in the FFT in the enclosure is reduced as well, and it's about 5-6 mHz in the spectrum I took. Stability will probably take longer with the ADR1399 because I expect the board will dissipate about 50% more power with it.

[Kleinstein]

The temperature shows still some "periodic" part, with a bit under 1000 seconds period. Is this an external temperature variation, e.g. from the heating / AC system ?
I have seen temperature oscillations inside a case, but this was considerably faster (more 10 seconds). So I don't think it is this.
There seems to be some part in the voltage reading with a similar frequency. So there could still be some thermal part to limit the stability.

The LTC6655 reference should be good enough for most purposes. The amplifier and scaling before the ADC has quite some resistors to effect the gain. So the advantage from a super stable reference would be limited anyway. At least with a gain of 1000 and likely still a gain of 100 the meter is limited by the amplifier noise, not the ADC or reference noise.

Higher power does not directly translate to longer settling time. It is more the heat capacity and thermal resistance to set the speed. The regulated temperature in the ADR1399 would more speed up the time needed to reach a stable temperature. Higher power may need more time constants because the difference from cold to hot is larger.

[CurtisSeizert]

The periodic part of the temperature is, as far as I can surmise, the fan cycling on and off for the HVAC system. The reason for the ADR1399 is the gain of 100x (200 actually, including the ADC driver). The RTO noise density of all the analog signal conditioning is around 360 nV/rt Hz at that gain. For a full scale input, reference noise will dominate below 0.1 Hz with the LTC6655. Anyways, I have both, so we will see if there is a noticeable difference at some point.

Here's a capture during the day (I averaged over 20 s to make things a bit clearer). I turned the thermostat up 1 F around 12000s, and you can see that the board does react to the change in the first derivative, but there is no noticeable impact on offset voltage once the temperature settles. You can see some periodicity to the noise for the voltage. It seems to be lagging the periodic temp fluctuations by about 90 degrees.

[dietert1]

I had this first derivative temperature dependence, too, when looking at my low thermal EMF DIY relay scanner. In my understanding the effect is caused by temperature changes "creeping" inside the board and causing transient thermal gradients and thus EMV.
That scanner is well protected from ambient temperature changes, but does not have active temperature control. So i installed a precision measurement of the temperature and calculated the first derivative to correct the effect numerically. This improved residual EMF from some nV to a fraction of a nV. See: https://www.eevblog.com/forum/metrology/scannermultiplexers-for-voltage-references/msg3971414/#msg3971414.

Regards, Dieter

[CurtisSeizert]

That scheme for temperature drift compensation is what I hand in mind here, at least as an option. I figured that heat conducted from the edges of the board to the case would be more problematic, so I added isolation slots around sensitive junctions and removed the ground plane from the edges of the board. It would be interesting to see if the performance is better when it is supported by standoffs, but that would require putting it in a somewhat larger enclosure, which could also skew the results.

I have a reasonably functional interface up and running, so I can pause the acquisition, update the parameters, and restart it to see the impact, which is nice for automating experiments.

I made an interesting observation about the noise floor of the lower gain setting, and I haven't been able to figure out what exactly is going on. At the analog out, the RTI NSD with shorted inputs is around 1.8 nV/rt Hz, but the ADC readings showed higher, around 3.0 nV/rt Hz. I changed the ADC input switches so they were both connected to IN-, and I saw a similar noise density, scaled as if I were measuring something at the low gain setting. This was sensitive to sampling frequency changes, with it getting noticeably better going down from 520 kSPS to 500 kSPS, but going up again as I reduced the sampling frequency further to 400 kSPS. That made me think it was EMI from either the ADC reads or I2C, but I ruled out both. In the first case, I showed there is no impact on NSD from altering block size over a span of 4 powers of two, and in the second I just turned off the I2C bus.

I adjusted the parameters so I would only get one block per phase so that ADC reads would not interfere with sampling, as I can only do slightly more than 500 kSPS without NCS going high during the quiet zone for the next sample. At 1 MSPS, the NSD dropped significantly to 0.8 nV/rtHz (again, RTI as if I were actually connected to the chopper stage), and at 2 MSPS it went down even more, to 0.25 nV/rt Hz. According to ADI's calculator (for the AD4630), with my input RC filter, this is far to fast for the input to settle from charge kickback (at 2 MSPS, it is 54 LSBs with 68R/2.7nF, 3.5 LSBs at 1 MSPS, and 0.02 LSBs at 500 kSPS). I thought I must have been just seeing the RMS sum of input stage noise and ADC + driver noise at this point, but when I ran the acquisition as normal at 2 MSPS, the RTI noise was still significantly greater than at the analog out, about 2.5 nV/rt Hz. So there seems to be some interaction term here, but I haven't been able to get to the bottom of it yet. There is a pole-zero network in the feedback for that gain setting (the gain really needs to be 60 dB at high frequencies for stability), so aliasing could be a concern here. The poles of the filters for the ADC drivers are about 160 and 110 kHz.

I also found that both gain settings seem to benefit from running at much higher modulator frequencies with a greater number of modulator cycles per ADC switch cycle. The impact on residual offset jumping from 315 Hz to 7200 Hz is <10 nV, and a much shorter settling time of 4 us is required at the faster modulator frequency to get a good aperture ratio (It is about 0.92 with the settings I used at 7200 Hz). This brings the noise for the high gain down to 1.1 nV/rt Hz, which if you correct for the aperture ratio would be 1.06 nV/rt Hz, which is essentially the same as what it is in simulation.

I have also done some experiments with the input bias current by checking the change in offset by switching the relay that shorts a 10k source resistor. There is some impact with modulator high levels, with the highest setting seemingly the best. Consistent with my experiments using just the PE4140, the bias current is best when the switch just barely turns off. In this case, a low level of -40 mV was good (I didn't try 0 mV, and this is very close to the threshold voltage, which is around +30 mV). I do feel as though this would reduce the source impedance somewhat, but the NSD for 10k was right on the dot, so it hasn't been reduced catastrophically. Anyways the input bias current was around -1.7 pA at this level (i.e., the average reading was 17 nV lower with 10k than with a short). This is at 315 Hz. I will need to run more experiments to see if this is actually a good idea and also what the impact of deadtimes is. The relay switching the capacitor is stuck, so I need to replace it to see the impact of input capacitance.

[Kleinstein]

An input bias current in the 2 pA range would be really good for such a low voltage noise. There is however still a chance that adding the 10 K resistor to the input can have more effect than just from the bias current. The resistor could also change the settling, which may be an issue at least for the faster modulation and short dead time.

I am a bit surprised to see so much effect of faster modulation on the noise. Normally the JFE2140 and other parts should not have that much 1/f noise at 315 Hz and higher. Beside noise, it could of cause also be mains hum - the magnetic part is hard to shield.

[voltsandjolts]

Interesting topic but I'm an amateur at this stuff. Just a thought on transient thermal emf's.....if the PCB had components on topside only, it could be placed atop a copper plate to act as an iso-thermal block, perhaps with thermal conductive sponge sheet between them.

[CurtisSeizert]

Interesting topic but I'm an amateur at this stuff. Just a thought on transient thermal emf's.....if the PCB had components on topside only, it could be placed atop a copper plate to act as an iso-thermal block, perhaps with thermal conductive sponge sheet between them.

I had that thought about using a vapor chamber attached to the PCB with thermal epoxy for a nanovolt relay scanner card, but I hadn't really considered it for this because there are a lot of components.

An input bias current in the 2 pA range would be really good for such a low voltage noise. There is however still a chance that adding the 10 K resistor to the input can have more effect than just from the bias current. The resistor could also change the settling, which may be an issue at least for the faster modulation and short dead time.

I am a bit surprised to see so much effect of faster modulation on the noise. Normally the JFE2140 and other parts should not have that much 1/f noise at 315 Hz and higher. Beside noise, it could of cause also be mains hum - the magnetic part is hard to shield.

I don't know the reason why it would be any better at such high frequency. I am now in a better position to do systematic testing for such things, so I can map out the impact of modulation frequency on noise. I had initially tried higher frequency because it is above the zero in the feedback network at 101x gain, so the modulated offset signal would be fed to the ADC at a higher gain. It actually seems to have more of a relative effect on the higher gain noise, which does not have the intentional zero in the feedback network.

I am going to map out the impact of different parameters on things like the apparent bias current, but I am still at the stage of figuring out what matters before I setup a design to get a response surface. It seems that it will be feasible to null out the apparent bias current at a given frequency, but it does not seem that one code will give a null at all frequencies or what the relationship there will be. The impact is quite linear at a given frequency, so by measuring two points, you can probably get within 1 pA of zero in one or two tries. At 3600 Hz, the resolution in the limited space I explored was about 250 fA/LSB of that DAC. I guessed 485 would be close from points at 400, 500, and 600, and I got a bias current of 0.34 pA. That corresponds to uncanceled charge injection of about 0.1 fC per cycle.  It was dicier at 7200 Hz, but I managed to get it down to -2 pA. My hypothesis about this effect was that there is JFET leakage current that is not dependent on modulator frequency and dynamic current from charge injection. Presumably were the static component zero, the code required to reach a null would not vary much with frequency. That doesn't seem to match the data at this point, but I'll need more data to rule it out. I attached two plots of modulator low level DAC code vs. bias current.

The way the code is set up right now, it will automatically fill up each cycle will the maximum number of ADC sample blocks when you feed it a modulator frequency, settling time, ADC sample frequency, and ADC block size. I will add an option to suppress that so I can take quick bursts at a variety of points in the switching cycle. With the input 10 nF capacitor switched in, the bandwidth with the 10k resistor in is only 1.6 kHz, so at 7.2 kHz modulator frequency, there should not be much change. I did that experiment, using a block that took about half the cycle and put it at the beginning and end. In that case, the difference was not statistically significant. When the modulator frequency is less than the bandwidth, there almost certainly will be an impact of dead time.

[Kleinstein]

A combination of a fixed bias (e.g. leakage from FETs and diodes) and a net charge injection from the modulator sounds resonabel. The slope in the two curves with bias vs DAC value is close to the 2:1 frequency ratio.  A DAC value of ~ 490 to gets zero bias with 3600 Hz. At 7200 this would 2 fold compensate the static bias.  This would suggest some +160 pA of static bias.

The diodes and JFE2140 should not give that much leakage. So chance are it could be from the modulator FETs, that are made for RF performance and not so much for low leakage.

[CurtisSeizert]

A combination of a fixed bias (e.g. leakage from FETs and diodes) and a net charge injection from the modulator sounds resonabel. The slope in the two curves with bias vs DAC value is close to the 2:1 frequency ratio.  A DAC value of ~ 490 to gets zero bias with 3600 Hz. At 7200 this would 2 fold compensate the static bias.  This would suggest some +160 pA of static bias.

The diodes and JFE2140 should not give that much leakage. So chance are it could be from the modulator FETs, that are made for RF performance and not so much for low leakage.

I tested a couple samples of the PE4140s for gate leakage before designing the board around them. I got <100fA at -3V. They have minimal ESD protection (The HBM rating is 100 V), so there aren't protection structures to give additional leakage. I do need to just test the static bias by turning the modulator off still, but the reason why I don't think it is as simple as being able to directly compare the DAC low codes between frequencies is that if one repeats your analysis for more frequencies, the result for static bias is different each time. The zero-bias code change gets smaller each time you halve the frequency, until it remains essentially constant below 900 Hz. A code of 900 for both 900 Hz and 225 Hz gives an absolute value for bias current of <1 pA. There may be some frequency dependence for turn off behavior since the body is not tied to gate or source, so during the off cycle it is floating. I don't know definitively, but from what I can piece together from patents, the PE4140 is a 25 nm film-thickness FDSOI FET, and kink effects have been observed in such devices (https://www.sciencedirect.com/science/article/abs/pii/S0038110117308651), so perhaps that is a factor here, but that is just speculation.

There is also a significant effect with modulator deadtime, with longer deadtimes at the same modulator code making the charge injected per cycle increasingly negative. The correspondence is not linear, but with the limited range I tested, from 78-109 ns, the value was around 1-2 fC/ns. The noise performance is best at short dead times, but the effect size is small. It's only about a 3% reduction going from 93 ns to 31 ns. I did this with 0R source resistance, so I don't know about current noise. There is no impact whatsoever with demodulator deadtimes over the range I tested. If you plot the charge injected per cycle against the modulator low level code at all frequencies and deadtimes I have looked at, the value is -70 to -78 aC/LSB. I would need to randomize the order of experiments before I could make any statements about what impacts that. Also, the zero bias code at a given frequency is temperature dependent, which makes sense as the modulator gate threshold voltage is temperature dependent.

I have not been collecting temperature data because I have had some issues with getting the linked list DMA thing to handle the I2C reads, so I have been calling blocking functions to get the temperature data from the sensors, and this does not work well at high modulator frequencies because the SPI reads from the AD4030 have to be blocking (software NCS given the octoSPI woes), and it's much faster to poll for SPI transfer completion and pull the NCS high than it is to do the same thing with interrupts (680 ns vs 799 ns NCS low time).

[CurtisSeizert]

I have finally hooked up the NVM to start measuring some external voltages, and I can tell that it will be a challenge to maintain the performance of the internal short. The change in offset between shorting the inputs internally and externally is not much. With the modulator frequency at 1800 Hz and the ADC switches at 200 Hz, I saw 37 nV and 45 nV respectively for internal vs. external. There are Pomona low thermal EMF binding posts on the front panel, and I was using a piece of unfluxed solder wick as the short. However, to get decent readings, those binding posts need to be covered from drafts. The susceptibility to mains-frequency noise is much greater, unsurprisingly, though the situation with a short is not too dire when everything is closed up. I found that the powerline noise would just alias back to lower and lower frequencies when averaging blocks of samples if I used frequencies that were not a multiple of 60 Hz. I tried 315 and 1770 Hz, and they were a mess. With 1770 Hz, there was a peak at around 350 mHz.

Using a 49k95/50R divider, I measured some voltages from my power supply, and the issue was much worse. For some reason I cannot explain, the gain on both channels is 25% lower than what it should be from the schematic (I am using values of 2002 and 202 for the high and low gain settings). The issue does not seem to be with the chopper stage - on the high gain setting (1001x), I measured a gain of 1009 for the front end and 2020 at the ADC inputs. From the limited work I have done to diagnose the issue, I know it is unrelated to the sample rate of the ADC, as I get the same numbers with 500 kSPS and 2MSPS.

The additional inductance from putting a short at the front panel definitely causes some gain peaking for both settings. I think it would probably be best to slow them both down a bit by increasing the integrator capacitance from 47 to 68 pF and same with the feedback capacitance. As I was investigating this and running some simulations, I think I had conflated SPICE not converging with instability on the 101x gain setting. The pole-zero network in the feedback for that doesn't seem to be crucial (I took it out on the board too). The point where open loop goes >0 dB with positive feedback is at >100 MHz, and this does not seem like a real issue with the parts I am using because the diff amp and the ADA4625-1 just don't have that kind of bandwidth. The phase margin at 40 dB closed loop gain does leave a bit to be desired, but increasing the value of the caps as above should work. I think this is important because the increased noise from the low gain setting relative to the analog out is almost certainly related to aliasing, and having the gain go to 60 dB at higher frequencies was probably not helping. My general sense is that you need to take antialiasing very seriously with oversampled SAR ADCs at this kind of resolution. Clearly, it is not just the SAR ADC though, which is apparent from the low frequency spectrum with a 315 Hz modulator clock.

Speaking of aliasing, I looked at the noise from the PSU, and it is definitely a target for improvement. I think the +8V5 rail noise is making it to the analog outputs, but this is still at the level of a strong suspicion, and I haven't powered all the rails with linear supplies to confirm this. The noise spectrum of the +8V5 rail has a lot of lower frequency stuff (~10 kHz and harmonics, switching at 2 MHz). I took a spectrum of all the rails (attached) using a test board with some resistive loads. I know from some previous experiments that the noise spectrum of the +8V5 rail gets better with heavier loads, so I think that it is a combination of the controller going into burst mode and ring-off when the switch goes high impedance. I have made changes to the schematics for the next revision and have added another Cuk (not inverting) to power the ADR1399 heater based on Andreas's notes. It may be better to actually use the same topology for the +8V5 rail, as I was able to get very good efficiency in simulations while staying in CCM at light loads (of course, this requires very large inductors). I think that staying in CCM is crucial for this application because of the noise sensitivity, and the radiated emissions from ring off could easily alias into the pass band. I don't see a lot of high frequency content in the spectra for the primary rails supplied by the SMPS board, but I haven't checked around with an E field probe to see if there are radiated emissions coming from high dv/dt transients.

Ultimately, I don't know that it will be optional to synchronize the modulator clocks with the mains to get good performance here. I have an isolated input I can use for such a clocking signal, and I have designed a board to drive it. I am still learning about DSP, but from what I can gather, FIR filters, like a block averaging filter, will generally be susceptible to aliasing unless the spurious signal lands in a null. I feel like it would be helpful to use an IIR filter for the offsets to mimic what I did with the proof of concept version with Rs and Cs to reduce the susceptibility to noise, but I will have to test this. I have attached some spectra I took of the analog out and power supply. The modulator clock was 1800 Hz unless otherwise specified.

[Kleinstein]

For the curves with the external short one can see the expected extra low frequency noise. It is however not so clear how much of this may be coming from the scope. To really judge on the low frequency / longer time scale performance I would prefer to look at an Allan deviation plot from data taken via the ADC.

I think much of the extra frequency signals at higher frequency and maybe also some of the lower frequency ones could be from the scope sampling the signal all the time, including the switching spike of the modulator.

For the digital filtering the block averaging is best for white noise, but has the side lobes at higher frequencies. A more classic FIR filter can suppress the side lobes better, but at the cost of more noise bandwidth and thus more noise from close by. It would still help to suppress interfrerence from some higher frequency. I would prefer a filter still relatively close to the block averaging, with only somewhat smooth start and stop of the aperture.
I don't think the offset correction part should be that critical. In first approximation the offset does not contribute to a signal / noise below half the modulation frequency. It is more that the offset of the JFET amplifier can effect the current spike at the input and the switching transisents.

I agree that it can make sense to slow down the amplifier a little more. This could help with stability for the gain 100 (e.g. reduce ringing after the modulation steps). For the really high frequencies approaching 100 MHz the models for the transistors and OP-amp may not longer be accurate and parasitics can come in. A point that can change things is also the capacitance of the gain setting switches.

With a SAR ADC aliasing can be serious, but most of this should be handled with the ADC driver and filter there.
The other from of aliasing can be from the modulator.

[CurtisSeizert]

I am focusing on trying to get the ADC readings to make sense right now, and once I have done that, I'll take a long capture and make an Allan plot. I have generally found it counterproductive to troubleshoot with flawed analytical methods because it can become confusing to remember which conclusions one has drawn have an asterisk next to them. That said, the ADC data at high gain match the analog out quite well for small-signal stuff, so I have a couple spectra that show the increase in noise going from internal short to external short with covered terminals to external short with exposed terminals.

The reason I think aliasing is a big deal is because an integrating ADC (HP 3458A) shows an NSD that is 40% lower than the internal SAR ADC on the low gain setting. I am sure there are possible scenarios where that is not aliasing, but I would think that aliasing is the first suspect. That may help contextualize the motivation for getting those FFTs of the analog out from the scope - I wanted (among other things) to understand what spectral components could be the the root cause of this. In general, the fundamental at 8 kHz and its associated harmonics stay at the same level for both gain settings, and the peaks at the modulator frequency and its harmonics rise above the white noise more at the lower gain (compare the two attached spectra with dark backgrounds). I would guess that the increase in white noise density with the external short is, at least partly, due to the broadband noise aliasing back into the passband amplified by the gain peaking associated with the additional source inductance.

I cannot rule out aliasing as a result of the odd ADC readings as one of the input switch settings gives readings that are too low (not closer to zero - they are the larger absolute value with negative input voltages) and the other gives readings that are too high. For example, When I should be getting about 2.01 V, I am seeing codes that equate to 2.34 V and 0.67 V. Everything on the analog side looks fine, so I think this is probably a code issue (or a bad part issue). I mention this because if this is a difference in absolute values for the weights of each phase of the cycle, then spurious signals could also fold back over 1/2 f_ADCSW, though to a lesser extent than if one of the weights were zero.

[CurtisSeizert]

I fixed the weird ADC voltage thing. The SPI bus won't do 64 MHz unless you go to the highest power scaling setting, and bits were being shifted right by one position. I don't know how that worked with negative numbers, but anyways I am getting 1.0038 mV for something that my 34465A says is 0.9996 mV and same story with the polarity reversed. It is exciting when you put this much work into something and finally get it to the point where it can do something nominally useful.

[macaba]

Hi Curtis, i haven’t had the chance to keep up with this thread & hoping to find some time to read it however I get the impression you might have excess ADC noise? In which case, perhaps change your 2x input R to 4.7 ohm, change 2x CM caps to 100pF and add a differential cap of 10nF. This is a practical tip from my workbench, not theory.

Edit: if you short the inputs of your FDA to 0V (inputs of U36) and measure the NSD (scaling ADC values with reference voltage of 5V) then I would expect OPA+FDA+ADC NSD in the range of 20-30nV/rHz (ADC alone with short directly at inputs is about 18nV/rHz). If more then try the filter modification I suggested above for sure.

[CurtisSeizert]

Hi Curtis, i haven’t had the chance to keep up with this thread & hoping to find some time to read it however I get the impression you might have excess ADC noise? In which case, perhaps change your 2x input R to 4.7 ohm, change 2x CM caps to 100pF and add a differential cap of 10nF. This is a practical tip from my workbench, not theory.

Edit: if you short the inputs of your FDA to 0V (inputs of U36) and measure the NSD (scaling ADC values with reference voltage of 5V) then I would expect OPA+FDA+ADC NSD in the range of 20-30nV/rHz (ADC alone with short directly at inputs is about 18nV/rHz). If more then try the filter modification I suggested above for sure.

I am interested to know if my descent into madness comes through as you read the thread. Also, I appreciate the practical tip. I may try that out because the input filter does not have the bandwidth to support 2 MSPS operation (68R/2.7nF), and it should be beneficial to operate at a higher sampling rate to help with aliasing. Every time I rework this board I hope it will be the last time. The five or ten minutes of actual reworking turns into two hours or so between disassembly, popping off all the shielding covers, preheating, cleaning, baking, and reassembly.

I can actually just interrupt normal acquisition in a serial terminal and switch the measurement to have both ADC input switches connected to Vcm or the output of the chopper stage. I have done some experiments where I do that, and the results are the same regardless of which one I am measuring, but I will need to repeat those with the code fixes I have made. With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS. Those are provisional values, so I will repeat the experiment before I make any changes to the board.

I hooked up the bench supply to power the board rather than the SMPS daughterboard, and I found that the 8 kHz and harmonics that I saw before were indeed due to the SMPS as they are absent without it. I've included both spectra here. I still see some peaking in the response with the added inductance of the protection circuitry with the integrator and feedback caps changed from 47pF to 68 pF (see the NVM B External short spectrum). I may try to fix this by increasing the value of those caps even more. It isn't really clear to me that this is problematic with respect to ADC aliasing because there isn't really any difference in NSD when I increase the sample rate.

I have done some very preliminary linearity measurements, and while I have found the analog out to be linear to within experimental uncertainty, there are certain points where the ADC readings deviate considerably from expectation, often very near points that read fine. That makes me think it is a data processing issue. For example, there is a 1% decrease in gain going from 815 uV, which reads as expected, to 810 uV, which does not. My source is a 200k/20R divider using some discrete BMF through hole resistors I had lying around attached to various things that I can drive from a battery (or a battery itself), so I am stuck with measuring certain discrete voltages at the moment.

The ADR1399 board is up and at least partly running. The Cuk won't start up with the large initial current demands of the heater (it looks like about 140 mA), so I need to power the negative rail externally for the first ten seconds or so. The current draw at 15 V increases about 50% relative to the LTC6655, from 39 mA to 60 mA, and the noise performance on the high gain setting seems to be worse. I don't think this is solely attributable to heat diffusion, as the increase is visible up to about 10 Hz, which is probably too fast for thermal effects in a closed case with the shields on. The offset voltage is marginally higher than before, which probably is thermal. The increased heat from the reference accentuates the imbalances in dissipation around the input switch that are present in the LTC6655 board.

[Kleinstein]

The inductor at the input can pick up magnetic interference. Some of the noise in the 200 kHz range may come from a SMPS or AM radio.
So it may be more than just the added inductance. The added inductance could effect the settling after the modulator switching.

[macaba]

Curtis,

I tend to think that with any kind of ultra precision instrumentation project, a descent into madness is inevitable and perhaps even desirable! A certain kind of manic ultra-focus is sometimes needed at this level as a lone developer.

With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS.

Your reckoning seems about right to me, and your 58nV/rHz (assuming no calculation error) is further proof - I also saw an approximate doubling/tripling of noise until I fitted the correct charge kickback filter values. It seems the precharge circuitry on these ADCs simply reduce, not eliminate, the issue.

[CurtisSeizert]

Curtis,

I tend to think that with any kind of ultra precision instrumentation project, a descent into madness is inevitable and perhaps even desirable! A certain kind of manic ultra-focus is sometimes needed at this level as a lone developer.

With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS.

Your reckoning seems about right to me, and your 58nV/rHz (assuming no calculation error) is further proof - I also saw an approximate doubling/tripling of noise until I fitted the correct charge kickback filter values. It seems the precharge circuitry on these ADCs simply reduce, not eliminate, the issue.

Yeah, I had been putting in 12 hours a day in February, but I have slowed down a bit now. Most of my coding experience, and about 95% of my C coding experience has been writing high performance algorithms in CUDA, and that was about 8 years ago. Incidentally, that subtly gave me an aversion to flow control because branching statements are really bad when you're trying to keep blocks of threads coherent. Anyways, here is the data for ADC noise. For the LTC6655 board I fitted an ADA4805-2 as the ADC driver rather than a 4807 because it's a better fit for 500kSPS, which I had planned on using. As I mentioned, the RC filters are 68R/2.7nF, so at sample rates significantly greater than 500kSPS, the input has not fully settled (the bandwidth is ~850 kHz). According to ADI's tool, we're talking about a handul of ppms at 2MSPS, so presumably we can trust a couple digits of precision for these results.

500k: 381.0 nV/rtHz
1M: 348.4 nV/rtHz
2M: 42.8 nV/rtHz

The measurement conditions were a bit different, and I was relying on memory for the value at 2 MSPS, so both of those might be the reason for the discrepancy. The 2 MSPS value is repeatable to beyond the precision I gave, but the others are not. Interestingly, this does not manifest in an increase in LF noise in the spectrum as the 1MSPS and 500kSPS are both flat. With 2 MSPS, I do start to see some 1/f noise from the driver at LF (I only went down to 1 Hz, which is about the corner). All had an offset of about 33 uV. Note that all values are scaled to be referred to the input of the ADC.

It isn't clear to me why these look the way they do, but I haven't taken an analog spectrum of the inputs. I would assume there is noise at ~500kHz that is aliasing back, but I don't know what the source would be. Everything is under power with the bench supply, so there should be no switching noise. I also know that it does not come from activity on either of the SPI busses from previous work because disabling DAC updates or changing the block averaging of the ADC does not have any impact. I2C is routed nearby, but that was not active for these experiments. The UART is active, of course (that's where I got the data), but it is routed far away from anything. I suppose I'll have to get an analog spectrum at the ADC inputs to make sense of this.

@macaba - one final thing: what inspired that particular choice of values, and what driver were you using? Even if each driver is only seeing ~200 pF to ground, 4.7R seems like it might court instability.

[CurtisSeizert]

I took Mark's suggestion on the RC filter in front of the ADC, and it worked really well. I changed the values to 4R7/ 2.7nF CM + 10nF DM. The CM capacitance was chosen to limit the potential slew rate of signals at the terminals by keeping the RC time constant over 12.5 ns as mentioned in the datasheet. For the low gain setting, the NSD dropped from 3-4 to 1.51 nV/rtHz at 500kSPS and 2.5-3 to 1.50 nV/rtHz at 2 MSPS. It didn't really make sense to me that the NSD was as high as it was at 2 MSPS. Referred to the input at low gain, I was seeing about 0.3 nV/rtHz from the ADC + driver and reading about 1.7 nV/rtHz at the analog out but then seeing close to 3 nV/rtHz in the ADC readings. With the new RC filter here are the NSDs I got, referred to the ADC inputs:

fs = 500k; 55.40 nV/rtHz
fs = 1M; 43.66 nV/rtHz
fs = 2M; 35.94 nV/rtHz

If you plot the PSD against 2/fs for these values, by my math, the slope should be the square of the RMS noise of the ADC and the intercept should be the driver noise. The linearity with these three points is good (r^2 = 0.9998). If you extract the values from this, you get a driver NSD of 26.65 nV/rtHz and an ADC noise of 24.3 uVRMS. The driver noise is very close to expectations (LTSpice said 28 nV/rtHz), but the RMS noise of the ADC is about double what the datasheet lists as the typical value (12.5 uVRMS). The RMS value isn't just ADC noise though - it's also broadband differential noise at the inputs that can alias back into the passband as well as broadband common mode noise doing the same but reduced by the CMRR. The measured broadband NSD at the ADC inputs is actually matches the predicted value pretty closely without the 10nF DM cap, though that could be coincidental. I will probably try a simple 4R7/10nF (CM) for the version with the ADR1399 to see if that works any better. Either way, it seems that the values you would suspect should be fine (like 68R/2.7nF for 500kSPS and 33R/1nF for 2MSPS) leave quite a bit on the table. The predictions for system noise with ADI's online calculator do not match my results for those combinations with this topology, and the errors are numbers that are not convenient to express as percentages.

This is more of a general interest thing than of direct relevance to the NVM because 24 nV/rtHz at the ADC inputs is more than good enough to not impact the results with either gain setting. The mystery of the interaction between ADC noise and the input signal is still unsolved - note that here, the NSD at 500kSPS referred to the chopper input is 1.5 nV/rtHz though the ADC noise was greater than it was previously at 2 MSPS. My attempts to probe the input with a fast DC amplifier didn't find anything suspicious, but I was running into the noise floor of the instrument I used to get the spectra.

[CurtisSeizert]

I have gotten preliminary linearity results with both boards. The ADR1399 board looks good, the LTC6655 board not so much. I need to get my low-level source up and running to really figure out what the issue is with the ladder. I suspect it is related to intermodulation/aliasing as the points that were out of trend were also drifting a lot. I ran some long captures with both boards with the modulator frequency at 1800 Hz and averaging 30 cycles to get an output data rate of 60 Hz. A peak around 10 mHz was noticeable with the LTC6655 board, and I attributed this to the poor antialiasing performance of simple block averaging filters. I changed the code to allow higher order sinc filters (up to sinc3) because all the cascaded integrator-comb calculations can be done in fixed point. I ran a couple tests where I changed the ODR to 28.12 Hz (32 averages) to ensure there would be an alias of the mains frequency peak in the sinc1. The peak was not visible in either the sinc2 or sinc3 runs, but the sinc3 run had somewhat higher white noise density (about 10% higher), so I used the sinc2 filter for block averaging in another long capture with the LTC6655 board.

I got a bit more than 4 days of data before the BMS cut off the power, and the noise performance with the sinc2 filter was very good. The spectrum remained flat a bit below 1 mHz. There was a fair amount of drift (about 7 nV). I attribute this to the increased efficiency of the buck converters on the SMPS board at lower voltage. I did some regression analysis with time, input temperature, and the first derivative of input temperature as independent variables. I selected portions of the dataset where the correlation coefficient between temperature and time were low r^2<0.1 and got positive temperature coefficients of 0.25-0.6 nV/K. Obviously, this is not the best way of determining the tempco, but it is clearly quite small as there was quite a bit of temperature variability during the capture. The sensitivity to temperature change is between -1.5 and -2 nV*h/K. I think that both the drift and sensitivity to temperature change could be improved in a different case with the board supported differently. With the space taken up by 4x21700 batteries, there is very little extra room in the Hammond extruded Al case this was designed for.

The ADR1399 board does not seem to show the same downward drift as the battery discharges. I think this is probably because the increased efficiency effect is cancelled out by the increased current demand of the reference heater as the voltage between the heater pins drops. HTR- is supplied by the Cuk converter, so the associated components will dissipate more heat as the current increases. I included time domain plots and ffts for all these long captures. I RMS averaged the FFT data into logarithmically distributed bins to make it possible to see what is going on on the right-hand side of the plot.

I was underwhelmed with the performance of the Pomona low-thermal binding posts for this application because it really became critical to prevent air movement around them to reduce noise from transient thermal EMFs. I changed to a LEMO 0S size receptacle using the normal contact material, and that really helped. For some reason, it was also very helpful to put a CM choke at the input (just by wrapping the wires around an amorphous core to get about 1.5 mH). I don't have a shorting plug, but when I shorted the inputs at the end of a second receptacle and a length of cable, the offset relative to the internal short was about 200 nV, and that value seems to be reasonably stable.

I have identified a couple ways in which the protection on the power rails is inadequate, mostly by killing a couple AD4030s in fault states. In future revisions, I am going to add TLV431 + PNP clamps to most of the positive rails and increase bulk capacitance to prevent this sort of thing. The AD4030 (and probably the AD4630 as well) seems to be very susceptible to death. When the 1V8 rail had a transient overvoltage event from me accidentally shorting the +9V and +2V rails while I was probing the PSU (the latter supplies +1V8), only the ADC, two TMP117s, and the LDO died. All the glue logic and MCU survived unscathed. Also, the THP210 can actually pull the 5V4 rail above the absolute maximum for the AD4030 (I saw it hit about 6.5V) through the clamping diodes that limit the input signal swing. If the 1V8 rail dies, the ADC input switches do not turn off inputs above 5V, and that leads to another failure mode for the ADC. This is obviously problematic because any short to ground on the 1V8 rail will definitely lead to the death of the ADC.

[Echo88]

Maybe a variation of the overvoltage protection circuit figure 91, page 27 is also interesting in your rail protection case?
https://www.analog.com/media/en/technical-documentation/data-sheets/ada4177-1_4177-2_4177-4.pdf / https://opendcm.blogspot.com/2020/04/revised-analog-front-end-over-voltage.html
Cant remember if i already proposed it. I need to do some simulations on it myself, as it seemingly avoids the necessary transient reducing bulk capacitance.
Losing those high cost ADCs surely brings a tear to the eye. 

[CurtisSeizert]

When you lose one by shorting two pins while probing, it also brings some curses to the lips. I prefer to reflow BGA packages in the oven, so I had to take off a few of the though-hole compounds as well. No fun.

It seems like opencdm version of that protection circuit has an issue because it allows the input of the op amp to go two diode drops above the positive rail, but the idea in the ADA4177 datasheet is pretty cool. In this case, I think it will be easier to use clamps on the supplies as I mentioned because you only need one per rail (for the +5V4 rail) and you get protection against unforeseen causes of overvolting a rail, such as bridging two pins with a probe tip.

[CurtisSeizert]

I rewrote the firmware for the NVM in hopes of making it more understandable in the future as well as making general improvements and fixing some issues. One of the key issues was horrifically bad DNL (in the neighborhood of 1%), which had the feel of a firmware issue. The new firmware did indeed solve the problem, though there are still some bugs to work out that crop up with certain combinations of parameters. To test the linearity with the new firmware, I ran five 11-point sweeps from 0 to 1 mV using a source based on a DAC11001B and a resistor divider. The source INL should be in the <1 ppm range. The maximum linearity deviation I saw for these sweeps was about -1.5 ppm, which is a deviation of -1.5 nV from the straight line connecting the endpoints. I have attached a scatter plot for these preliminary results.

One of the issues I have run into with measuring external voltages is susceptibility to (probably) EMI, where simply attaching a cable, even if the inputs are shorted internally, increases noise and can affect the offset. I suspect capacitive coupling or leakage between chassis and circuit grounds, but I will need to investigate more. Once I find a way of getting better control over this, I will run some more experiments to get better linearity data.