1PPS errors with 33250A and 33622A arbs

[openloop]

Don't know if this is a known issue, so decided to post this:

As most of stories, this one started the usual way: a boy decided to calibrate his rubidium clock using GPS.
Method was chosen for its simplicity - take 1PPS derived from rubidium, 1PPS from a GPS module, connect to a 53131A counter measuring time interval between rising edges at CH1 and CH2.
The plan was to monitor the drift in 1PPS's arrival time over several hours and adjust rubidium to make the interval mostly constant (i.e. a flat-ish line on the graph) 

To get 1PPS from 10MHz I decided to use my good old 33250A using external clock connected to the rubidium generator.
But then a thought occurred to me: how do I know that 1Hz I get from the arb is really, exactly 1/10e6 of it's input frequency?

As a simple test I decided to measure again time interval between rising edges of sig gen's 1PPS and it's own 10MHz. While it will not guarantee correctness of 10e6 divider, it must at least be constant.

And... Drum roll...  It's not!

Both of my 33250As (of different ages) have the same glitch: they slip by 20ns (one clock cycle of 50MHz) every 3368 seconds. I.e. the graph is a stair case instead of a flat line.
Curiously, the same 33250A, when configured into "Pulse" mode, did not drift. At least not during several hours I ran the test.

Then I started to test other generators I have access to:

Stanford Research's SG384 is as cool as a cucumber: no drift, flat graph as it's supposed to be.   

Keysight 33622A: drifts like crazy. Much worse than 33250A. I didn't even bother measuring.

One would think that due to importance of 1PPS those guys will take care to set divider correctly, but no, as long as it's in spec it's "good enough".

[mendip_discovery]

Why not just take the 1pps signal from the GPS ref rather than faffing with extra units?

[Xiphos]

Any more info on this issue?  I am interested.  It sounds like a carry-over error from dividing but I agree, it should not be occurring…

[Renate]

The Keysight 33250A is using a 48 bit DDS phase accumulator.
The clock is 200 MHz (phase locked to a 10 MHz reference when used).

The frequency resolution is:
200 MHz / 2^48 = 0.000 000 710 542 736 Hz

So to generate 1 Hz we need an addend of:
1 Hz / (200 MHz / 2^48) = 1407374.88355328
See that 0.8... at the end? That means that you can't generate 1 Hz.

But you can generate:
Addend = 1407374: 0.999 999 372 2 Hz
Addend = 1407375: 1.000 000 082 7 Hz

Your phase is not going up in steps, the measurement is quantizing to 20 nS (50 MHz clock).

Of course these value are also affected by the digital frequency calibration values which go into picking an addend.

To demonstrate this all, set the main output to 10 MHz and XY scope compare the phase with the 10 MHz rear panel reference out.
You can't generate 10 MHz either.

In short, make your own 7 stage decimal divider.

[Xiphos]

Thank you Renate for your explanation.  However, we should discuss which signal generators are best at dealing with fractional division.   For instance, the SRS model mentioned uses a unique method where they choose a divisor close to the correct frequency and tune a VCO to PLL lock to that frequency.   It is a brilliant method.  Also, their latest clock generator, the CG792 does a FOM based frac-N choice. 

In any case, who has experience with other methods of signal synthesis that work better?  There are a number of other designs for synthesizers that deal with this problem quite well.

[Renate]

In any case, who has experience with other methods of signal synthesis that work better?

Well, what is better? In what way?
Want to make a nice linear sweep? You can't beat DDS.
Things with PLLs are not going to work so swell.

Instead of using a 200 MHz clock, you could use a different clock.
Just put in your (arbitrary) requirements.
"I want to be able to specify milli Hertz exactly".
Ok, what is the highest n such that 2^n / 5^3 is less than (an overclocked) 200 MHz.
137,438,953.472 Hz would work.
Can you overclock to 274,877,906.944 Hz ? Probably too high.
So using 137.4 MHz each 2048 of addend is exactly 1 milli Hertz.
You could also specify 1/2 milli Hz, 1/4 milli Hz ... 1/2048 milli Hz

For micro Hertz 2^n / 5^6 -> 140 737 488.355 328

Of course this is all going to wreck locking the clock to any reference.

For most people, micro Hertz is enough.
Of course comparing lab references with that isn't sufficient.

Indirect frequency synthesis uses lot of oscillators, mixers and filters.

[Xiphos]

ok, fair you are right there are a lot of applications with different optimization criteria.  Analog devices for instance has a few good notes on picking between frac-N and integer and straight DDS issues, etc. 

Regarding the OP and the "drift"....that really shouldn't happen though as the modulus should be compared to the signal and nulled if it goes off phase.  I think one of the ways the pulse mode on 33250a is better is it is probably integer counting cycles.  (I don't know the design I am just guessing.). If it works, then use it in the pulse mode.

The conclusion is those instruments are fabulous (especially the 33622a---I love mine) but not the right metrology grade instruments for frequency analysis synthesis.

[Renate]

The 33250A is 48 bits at 200 MHz and can get you within a micro Hertz res
The AD9850 is 32 bits at 125 MHz for 30 milli Hertz res
The AD9833 is 28 bits at 25 MHz for 90 milli Hertz res

Of course if you run the clock of the AD9833 slower you can get a micro Hertz res.
Mmm, run it at 268 Hz???