Electronics > Metrology

Lowest drift, lowest noise voltage reference (ADR1000AHZ)

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chekhov:

--- Quote from: branadic on March 08, 2024, 10:33:50 am ---Thanks Andreas. I haven't posted recent results for a while as we were waiting for our paper A 10 V Transfer Standard Based on Low-Noise Solid-State Zener Voltage Reference ADR1000 to be published.

--- End quote ---

That's great to have such paper, branadic, very helpful for young ADR1000A player like me, however I see it misses some very important initial conditions/hints from my point of view.
When I first time tried to find a top of TC parabola, I found that chips from my batch were likely made specially for Antarctica or so because their top is I don't know where ...
Playing with Iz had no reasonable effect.


Then I started looking at Q1 Ibias, which was already mentioned in this thread, but I haven't expected that I had to change appropriate resistor R2 so much - below 20K for my chips. LTSpice gave me a clue that in range 10-20K there is chance of TC to cross zero, so I finally made a few experiments:


With those changes now I at least have some hope.
I was applying constant current to the heater in 1mA steps manually for this time. For my setup Iz at zero TC points was around 4.5-5 mA.

Would be great to hear whether other folks have same issues or they have better chips in their hands. I tested only two available to me, in socket.

Andreas:
Hello,

Interesting that LTSPICE can simulate the zero TC temperature.

I had 18k6 for a zero tc setpoint temperature of ~55 deg C on one sample (the other sample #2 is built like data sheet cirquit).

https://www.eevblog.com/forum/metrology/lowest-drift-lowest-noise-voltage-reference/msg3921830/#msg3921830

I usually inject a voltage via a resistor to the setpoint voltage divider to sweep across temperature.

with best regards

Andreas

MiDi:
Has someone measured the voltage sensitivity to changes in the different resistances for ADR1000 as done for LTZ1000?
Would be interesting to see the changes w/o and w/ zero-TC compensation.
It was mentioned that it should effect the sensitivity for the heater setpoint divider R4/R5.

There is another method for zero-TC compensation: set R1 to 100Ω and add ~17Ω on top of the zener.
Is that only applicable to LTZ1000 (non-A)?




--- Quote from: Andreas on January 04, 2022, 06:47:19 pm ---after playing with the suggestion of Kleinstein here the results:
- the T.C. trimming is now symmetrically to a center value near 25 deg C.
- I had to fine trim the suggested 22K resistors which where already a good estimate to 18K4 to achieve this.
- what I had not expected is that the sensitivity is about halved. So I had to reduce R10 from 1 Meg to 470K.



--- End quote ---

Do you have already build and tested this approach?
It looks very attractive because the precision 1.5 multiplier gets you near 10V and the following gain stage has much lower sensitivity to drift of the resistors.

Andreas:

--- Quote from: MiDi on May 20, 2024, 09:36:45 am ---Do you have already build and tested this approach?

--- End quote ---
Hello,

no not up to now. (I obviously have more ideas than fit into my hobby time).
And perhaps one should combine that with an ageing compensation for the ADR1000 to get full benefit of the LTC1043 stability.

with best regards

Andreas

dietert1:
A scheme using an on-chip pn-junction (Ube) for temperature compensation is much superior.
The resistor divider 17 and 100 Ohm adds some gain to the -2.1 mV/K of Ube and it can be used if the positive temperature coefficient of the zener is a bit large. This is the case with the LTZ1000 that can have about 50 ppm/K = 0,35 mV/K left at room temperature (after compensation by Ube). Thats is 1/6 th and determines the resistive divider.
With the ADR1000 there remains less to compensate or the difference may even have the other sign. So one needs to use a different divider or even another circuit to reverse the sign, still using a temperature measurement from the other transistor on the chip.

Regards, Dieter

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