Electronics > Metrology

Nanovolt design challenge - build and show your own nV-meter in 256 days

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ch_scr:

--- Quote from: branadic on October 15, 2021, 09:28:24 pm ---[...]
Unfortunately, some of the really interesting FETs are obsolete these days, such as 2N5564/NPD5564 or BF862, [...]

-branadic-

--- End quote ---
Well there is LS5564 from "Linear Systems".
https://www.linearsystems.com/lsdata/datasheets/201187%20-%202N5564%20Series%20Rev%20A3%20dated%202017%2003%2003%20-%20Jaime.pdf
Sure it's not cheap and very much single source but you can (or could?) get a newly made 2N5564 equivalent.
At least about 2 years ago when I bought some for a repair. They are not advertised in the new catalog so not sure.
Even if not, they certainly have the LSK389A which is lower current but also lower noise and with slightly better matching.
I had a very good experience with their german rep "Ingenieur-Buero-Fluck" buying as an individual.

macaba:

--- Quote from: Kleinstein on October 16, 2021, 09:59:05 am ---For the with a chopper in front the requirements for the amplifier are less stringent. The target than would be more like 0.7-1 nV/sqrt(Hz) at some 1 kHz. There are a few FETs to choose from and one can get away without good matching and possibly even with just 1 pair.
The amplifier gets even less demangind if one goes with the chopper - transformer - amplifier configuration (e.g. like the EM nV preamplifiers).

--- End quote ---

Makes sense, the main reason I'm planning on JFET input (with optional CDS mode, aka "chopper") is so I can have switchable 480uF/100k HPF before it so that eliminates most input types.

macaba:
I have been simulating various input stages.

One concept that is novel to me is the idea of using the same input stage for the entire range from 10V to nV rather than switching between 2 parallel paths. I've come up with a solution but it has a rather high BOM cost; using discrete JFET follower (with fixed power dissipation in JFETs) on the frontend of low noise bipolar opamp (and the expensive design choices that follow from that requiring the next amplifier stage to also be low noise).

I am wondering if anyone has seen/could share successful examples of:
- Switching the JFET input stage between follower and gain configurations (i.e. switching between "resistors above" and "resistors below" and switching opamp inputs around).
- Compensating the JFET gain arrangement successfully to work as unity gain (I just can't seem to get a stable arrangement of RC compensation in simulation).

Kleinstein:
I got at least the simulation stable also with a gain of 1. The compensation may have to be more than just simple dominant pole, but with a 2nd step somewhat lower. This is kind of needed when one has very high loop gain. The input amplifier in the R6581T could be used as an example.
One may have to switch the compensation with gain.

One could consider less current for the JFETs when using a gain 1. This also reduces the gain of the JFET part.

I think that directly switching between an long tailes pair and source followers is tricky, as the switches add possible thermal EMF, resistance and unwanted capacitance.

I like a seprate preamplifier stage for the highest gain for 2 reasons:
1) one does not need gain switching at the input and avoid the swith there
2) the FB divider can be lower resistance and sees less self heating when the output of the first stage is lower (like 100 mV).

A parallel input stage for the higher voltages mainly needs a way to isolate the low voltage input - the higher votlage input can have it's own protection and input MUX. These parts are relatively non critical.

jbb:
... you know, it's horribly boring but the ADA4528-1 in G=+100 configuration is an option for the 100uV range:

* Vos < 3uV
* Drift < 0.015uV/C
* Noise ~6 nV/rt(Hz)
* Noise ~100 nV p-p 0.1-10Hz
* Ibias <= 600pA (over temp)

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