Prema BK7 derived meter

[Kleinstein]

The control for going from a negative ref (integrator output goingup) to a positive ref. is still a bit chaotic. For a good result an low noise one would want a rather stable waveform, as the integration time and all possible raw data points used fron inbetween are effected by the scattering.

Using only a limited part of the range (like 20 V of a theroretical 70 V) can help with stability of the feedback. How the the upper switching triggered ?

[dietert1]

Yes, it can't stay like that. When the integrator runs into the upper limit or only into the nonlinearity the measurement will be lost. For this test the rundown starts at a fixed time in the 10 msec cycle (middle + 1msec). Input integration is continuous like in the Prema. During rundown it integrates the difference between input and reference current.
Maybe i should add an upper comparator, something simple just to keep the integration cycle in order.

Regards, Dieter

[dietert1]

Meanwhile i wrote a simulator for the Prema integrator, assuming the simple control mentioned above and an upper integrator saturation voltage of 17 V. In my build the integration cap is 220 nF, so it reaches higher voltages. The diagram shows the simulator plot in a run of 0.5 seconds. The run starts with Integrator = 0 and with I unknown / I ref = 0.3. At 0.1 0.2 and 0.3 seconds into the run the input current gets raised to 0.4, 0.5 and 0.75. While at low input current the integrator is well behaved and settles for a regular cycle, the first integrator saturation happens at 0.4. At 0.5 and above it gets wild, with the last setting similar to the scope dump i posted above.
The PREMA 6048 runs below 0.3 (21 V / 70 V).

Regards, Dieter

[Kleinstein]

It is some time since I looked at the feedback and I faitly remember that there is kind of too much FB gain to make it stable. The solatron meters use the extra forcing signal added to the integrator. This is equivalent to having time dependent switching points, e.g. adding the negative of the forcing signal to an integrator for the other side of the comparator. With enough slope in the time dependent limit one should get a reduced gain and a stable feedback loop. The positive thing of applying the forcing signal to a separate part (e.g. some integrator or maybe a passive low pass) is that any error would not add to the integrator and the swing of the integrator is not reduced. One may also have more freedom (e.g. maybe use more than a simple square wave to start with, a 2nd capacitor for more rounding) approximating the ideal limit curve. It does not have to be perfect, just close enough to keeping the loop stable / well dampened.

Another possiblity would be to add some delay to the feedback: so switch the reference at least at one end with a delay after a level is reached. With the rather slow modulation there should be time to do the math to get a stable waveform.

[dietert1]

Yes, the force method appears to be a trick. Using only 0.3 of the available input range isn't that convincing either.
Rather i will try a more PWM like compensation method where one looks at more than one cycle before changing the PWM ratio. Maybe it is enough to make the PWM pulses symmetric within the time frame.
Certainly one needs a simple upper comparator to protect the integrator from saturating. Input voltage change or AC will then disturb the timing but valid measurements are guaranteed.
Anyway with continuous integration the integrator zero events won't exactly match the requested integration time. So the final result calculation needs interpolation at the start and at the end of each requested integration period.

Regards, Dieter

[iMo]

Could you point me to a schematics of that ADC? I'll try to sim it in LTspice (as I did years back with the Multislope)..

[dietert1]

Schematics of the Prema 6048 can be found inside the PDF user manual that is online, Fig. 11.8. They are using a proprietary control chip "BK7". It implements a mains PLL and a pretty simple integrator control method described in the user manual, paragraph 1.2. The P6048 front-end converts input voltage to input current using a buffer and a set of range resistors. Then the idea is continuous integration of input current compensated by a switched reference current source of opposite polarity (a PWM DAC). They implement a 10 msec cycle derived from the mains PLL. At a certain time in the cycle they turn on the reference current (begin of run-down) and count the time until a comparator signals integrator = 0 V (end of run-down). Summing up those time measurements they arrive at a high resolution measurement of input current.
My circuit is similar, though it uses a 14.2 V reference with two LTZ1000 and the reference current source is implemented following the Advantest R6581 design. Also i added some mods from a nonlinearity study in the Prema 6048 teardown thread. In my case integrator control is implemented in a Spartan 6 FPGA, with flexibility to change/improve the rules and calculations.
After that integrator saturation/instability problem i wrote a little simulator to understand what is going on and to test different control methods meant to solve that.

Regards, Dieter

[dietert1]

Meanwhile i found a better solution for continuous integration, using an upper comparator to avoid integrator overflow/nonlinearity. The integrator cycles independent of the rigid timing scheme the Prema 6048 uses. But timing can still be locked to mains in the sense of a PLL. This happens by the adjustment of the PWM ratio as seen in the simulation. x-axis of diagram is time in seconds. The 15 V upper comparator triggers twice during simulation. The maximum integrator voltage reached at I input/I reference = 0.5 is 14.67 V.
Next step is to implement this in the FPGA using fixed-point arithmetics.

Regards, Dieter

[Kleinstein]

I don't see how a comparator at 15 V would help if the level is essentially never reached. A comparator at a low level, like 30-50% could help, by using the timing as additional information to get a first estimate and from that calculate the time when to best switch from sising to falling.  To simplify the math and make it less sensitive to noise, 2 comparator levels (e.g. 50% and 10%)  for different ranges could be an option. The cost for an extra comparator is relative moderate.

[dietert1]

The upper comparator avoids invalid measurements when allowing I input/I reference > 0.5. The solution i am showing is almost as simple as the Prema 6048 yet makes better use of the hardware. At full range input the boards i made will run at a PWM ratio of 0.93.
The exceptionally long integration after stepping to 0.95 yields a valid measurement equivalent to several "normal" cycles.
Of course one can always dream up something more and you are invited to present your ideas in a more formal way. Maybe i will later look at it - once the DSP got implemented inside the FPGA and i can see how everything works out. The PWM calculation needs to complete during run-up, that is within 500 usec at a PWM ratio of 0.95.

Regards, Dieter

[Kleinstein]

The C code indeed looks relatively simple and may be FPGA compatible. So the 15 V comparator is only there to avoid the overflow with large steps. Chances are the system may have problems with higher levels of hum. This may already be an issue with the old prema system.

[dietert1]

Currently i am making the TEC oven for the second prototype. Image roughly shows thermal scheme. The copper heat conductor gets glued to the TEC and screwed to the heatsink. PU foam isolation near the flat cables is in two 2 cm layers.

Regards, Dieter

[Kleinstein]

The copper part may add some thermal resistance that could be relevant in comparison to the size of the heat sink.
It may still be OK as the peltier element is likely used with relatively low power, well below it't nominal rated current / power.
One may want a temperature sensor also on the outer side of the peltier element to make sure not to run into a thermal runaway when the heat sink a blocked. In this case the regulation could run away to a state with high current, trying too cool and overheat the heatsink. The outside sensor would also improve the regulation speed, as variations in the hot side temperature are likely the main path to get thermal coupling from the outside. In minimal solution would be to limit the peltier current to a safe limit, that could be something like half the nominal current.

[branadic]

Maybe I've overlooked it, but why did you choose temperature stabilization of the circuit with a TEG instead of temperature compensation in software?

-branadic-

[dietert1]

One disadvantage of a TEC oven is the thermal link to the outside, while a resistive heater oven can be made with much better thermal isolation, limited only by power consumption inside the oven.
The double TEC element was selected as it has less cooling power and higher heat resistance. So it can reach the same temperature difference with less electrical input. The copper bar also adds some heat resistance. It is made from ETP copper with about 400 W/(m K) heat conductivity, has a cross section of 4 cm² and an effective length of about 8 cm. That gives a heat resistance of 0.5   K/W. The Fischer SK 42/100 SA heatsink is specified at 1.65 K/W. Maximum electrical power into the TEC is about 5 W, so the device is safe.
Yes, a second NTC sensor on the heatsink can help yet requires digital control. I have a working implementation of that for our 19" temperature chamber. For the time being i implemented the meter oven with analog control, and it is good for about +/- 0.1 K. That already helps in comparison with the usual ambient temperature variations other meters are exposed to. The thermal mass of copper bar and aluminum enclosure slows down ambient temperature changes.

This is a study. There is a good chance it performs better than a meter with temperature compensation. A meter is made of many parts and there will be different delays for temperature changes. Calculating the correction requires the determination of the kernel of a convolution. And then there are nonlinear temperature drifts. In the end it may be cheaper to put the meter into an oven than to install a professional air conditioning system for the lab.

Regards, Dieter

[branadic]

Next question, did you copy the functionallity of the BK7 chip completely? Does that mean you have the very same slow integration cycles as in Prema 6048? I'd like to learn more about your work.

-branadic-

[dietert1]

A voltnut easter egg:

The BK7 contains certain elements i did not replicate for my meter study. E.g. it has a built in switched voltage reference to implement the integrating meter with just one additional opamp. The temperature measurement on the Prema 6048 processor board demonstrates this.

I kept the idea of polarity switching at the meter input, so the ADC handles one polarity only - with some overlap at zero. I added a third relay for rapid nulling of the meter. The Prema 6048 requires manual insertion of a low thermal EMF short. That procedure takes several minutes.
I also kept the idea that the front-end should be as simple as possible, essentially just a buffer amplifier with a resistor for voltage to integrator current conversion. As in the Prema 6048 this is implemented in a four wire scheme to eliminate influence of the range switches.
For my study i implemented the switched current source of the Advantest 6581 with SD215 switches, except i used a double LTZ1000 reference to have 14.2 V (+17 V in the 6581, U209). This change was motivated by the reference switching problems of the Prema 6048 which affect its LTZ1000 reference (linearity issue at low input).
I kept the idea of uninterrupted integration with a 10 msec cycle time. As we know the Prema 6048 ADC could measure about 70 V in its 20 V range, except above 25 or 30 V the integrator cycle becomes unstable and overflows can occur. I found an improved integrator scheme with a second comparator that avoids a 3.5x headroom (see above).
Another improvement over the BK7 is supplementing the precision comparator by a high resolution fast SAR ADC in order to perform noise filtering in the digital domain. This method can produce similar results as a multi-slope scheme. Multi-slope is incompatible with continuous integration.
With nowadays parts it's easy to count at 50 or 100 MHz instead of 3.8 MHz, so the meter has better resolution - roughly 1 ppm per cycle or 10 ** -8 in one second. Locking the measurement cycle to mains frequency can be all digital now, so the RC-oscillator time base of the Prema 6048 got replaced by a crystal oscillator (lower phase noise).
I want a voltmeter that runs at about 1 or 2 W of power, more than those integrated delta-sigma converters have available. So one can work at higher analog signal levels. 1 or 2 W is little enough to run the board inside a TEC oven. Hope one can get sub ppm precision without custom made resistor arrays, nor the hermetic precision resistors of the Prema 6048, nor a sophisticated temperature drift compensation scheme.

What i don't like about the Prema 6048: Nobody knows what is their temperature compensation scheme and we cannot check their method nor recalibrate that. Whatever hardware mod you apply can destroy the temperature compensation. Therefore i pulled the temperature measurement BK7 from our Prema 6048 and instead inserted a SHT35 sensor into the meter. I calculate the compensation offline.

Regards, Dieter