"NU180" - A U180 drop-in replacement for the 3458A.

[DB4UCH]

We may need to hold Vdd2 constant while varying Vdd1 as well, to separate out the two. But Vdd2 is much more likely to bear responsibility. If it's the main culprit, I think regulation could help, and that's pretty easy to do.

Yesterday I took some measurements to investigate this further: I powered VDD1 and VDD2 independently using two Agilent 6612C PSUs. The supply for VDD1 was directly connected to the NU180 and the supply for VDD2 was connected by connecting the positive output to the slope voltage selector on the NU180 and the negative to the cathode of CR155 on A3. (Base point for GND2) I then kept one supply constant at 5V and swept the other one from 4.5 to 5.5 V. I did this while measuring a short and a ~10V reference.
I attached the plots from this measurement below, the voltage in the filename is the one being varied.

While some effect is visible, I don't think that the magnitude of the zero-point variation is adequate to explain the difference for different NPLCs.

Greetings,
Simon

[Zondar]

While some effect is visible, I don't think that the magnitude of the zero-point variation is adequate to explain the difference for different NPLCs.

Good work. It seems that Vdd2 is responsible for the majority of the sensitivity as expected.

What is your verdict on whether the sensitivity is problematic enough to try improving voltage stability? You were torturing it a bit, so the real-life potential variation will naturally be less.

(P.S.: CMOS does not have "collectors", they have "drains," hence Vdd is usually used for CMOS rather than Vcc. A hard habit to break, perhaps.)

Edit: Looks like roughly 20 uV output change for 1V variation? I measured about 0.2 mV sag between conversion and the AZ phase when measuring 10V. That would correspond to about 4 nV output change due to the sag. The peak (pessimistic) change, between readout and AZ, was roughly 1.5 mV, which would correspond to about 30 nV change in the output. If my math and logic is right, this problem is below the resolution of the 3458A.

[hanzhu]

I understand the point about the negative voltage. I looked at those signals and indeed they barely budge from zero. However, given that HP included a negative supply, which I agree with for what that's worth, I feel it should be included until proven that it's not needed. Also, I'd expect the switches to perform a little worse if we really are right up against a rail.

Anyway, I updated my V0.5 design to include regulation for the positive side, e.g. 2.5-4.5V, with the option to use Vdd2 as-is. The CPLD would be fine, as the SN54LVC574 flip-flop, for example, allows operation down to 2.5V (2.2V, actually) with 5V tolerant inputs.

I'm still thinking about the negative side, but one option is to allow switching from GND2 and a negative regulator, maybe the ADP7182, with a flying lead to -18V. It would be easy to hack that to try 0V only (I'd have to cut a pin to try it now).

Using +/-2.5V could provide a tiny improvement in linearity and on-resistance over the current +4.4, -0.6V.

I recommend an LDO chip: TPS7A3901DSCR

[Zondar]

I recommend an LDO chip: TPS7A3901DSCR

Thanks. Yes, that one looks good, but the package would be more difficult to hand-solder. I don't think it comes in any others, unless it's with a different part number. Also, LDO doesn't matter at all if you are going from -18V to -2.5V, though other specs like noise and PSRR may be better.

Do you know of any that can regulate below 1V? I haven't found one. Most won't go lower than about 1.2V.

Also, regulators will droop a little under load too. So I'm not even sure we would come out ahead. But regulating Vdd2 is easy (GND2 is harder), and it could be tried. I'm still interested in whether using +/- 2.5V could help, though, as there's less of a slope about zero in that region, and the resistance would be slightly lower as a bonus (note: can't test this unless the FF's run on 2.5V as well).

Ultimately, from Simon's and my measurements, the effect on the digitized output due to variation under load appears to be so small that it might be ignored. What do people think?

[DB4UCH]

I did some more investigation related to the zero issue (mor details about what the zero issue is are attached below (from a PM to Zondar))

As I wasn't yet able to find anything that influences this behavior I tried to see if it follows some pattern. I therefore increased the NPLC from 10 to 100 in steps of 10 and took a datapoint at 200 NPLCs and plotted the difference in zero point. (plot attached below)
The relationship of NPLC from 10 to 100 regarding the zero-point seems to follow some sort of 1/x or exponential function. Above 100 it doesn't change anymore It still changes, but with lessend impact. The reason for this is still unknown, but maybe some of you have some ideas. (I hope it's not something in the FW of the 58A)
Forcing longer intergration times with APER, doesn't show this effect.

Greetings,
Simon

Here is my description of the Zero issue:

The "zero-point issue" is that with the NU180 the zero point (so measuring a short) shows dependence on the measurement NPLC. So, while the zero point for 1 and 10 NPLCs is identical in my case, taking the measurements at 100 NPLCs shows that the zero point has shifted by somewhere between 0.5 to 1.2 µV in comparison to the 10 / 1 NPLC case. (The variation has so far only shown dependence to time, so might just be influenced by noise) Investigating lower NPLCs than 1 doesn’t really make sense as the LSB is then larger than the deviation.

This behavior doesn’t appear in the real U180. If this issue violates the 3458A specifications I don't know. The zero point is in spec nonetheless, but the error is in the order of magnitude of the transfer / linearity spec. (which is only specified for "using accepted metrology practices" so likely 100+ NPLC)

As for how I evaluate it:
I connect a good four wire short to the input and then, over GPIB, take the following measurements: (PRESET NORM, AZERO 1, OFORMAT ASCII (although with PRESET FAST and OFORMAT DINT the issue also exists.))
Take n readings at 1 NPLC (n = 1000)
Take n/10 readings at 10 NPLC
Take n/100 readings at 100 NPLC
I then take the mean of each block of readings and repeat the whole measurement block to lessen the impact of thermal zero drift.

To evaluate the issue, I then subtract the means of 100 / 10 NPLC from 1 NPLC and eventually mean those differences, too.
I then can evaluate the results.
Wanghar has also verified that this behavior exists. (Although he has seen it only over GPIB, while I think that just from front panel readings one can't really evaluate it)

P.S. I also thought I had a solution to this problem, but this one just shifted the issue to the 10 / 1 NPLC case.  (+ This only "worked" on the primitive NU180 without FFs)

I have investigated a lot of things to change this behavior, but I was unsuccessful. Neither timing, supply voltages, the zero glitch jump circuit, mains synchronization and NU180 revision show any sort of change.
I am now trying to see if there is a way to mathematically model this difference depending on NPLC, to maybe get some introspection into what effect can cause this. (I hope it's not some mathematical correction in the FW that is specific to some U180 problem that we might have fixed / made worse with our NU180.)

[Kleinstein]

It is odd to see a difference between 10 PLC and the longer times. AFAIK the 3458 normally does the longer integration by averaging over multiple 10 PLC conversions. There is some way to get longer integration at a piece, but that mode is more noisy and rarely used.
I don't know if the averaging is done on A3 or only at the output side. There seems to be at least some extra delay when a 100 PLC conversion is complete. This could be some data transfer.
The delay alone could have some effect from some settling effect. However I see very little reason why the original U180 / NU180 would be much different in this aspect. This would also be 2 readings at essentially zero, but the transients from the precharge part and gate charge compensation can be slightly different.

A point that can have some effect could be the data transfer via the fiber. This uses quite some current and may cause shifts in ground and the 5 V supply.
The NU180 may be a bit more sensitive to the voltage. For testing the VCC effect one would have to look at the non AZ mode too.

Most NU180 versions don't use the supply modulation, but they still need to connect the sense part somewhat with a short.

A way to get some slow settling ( following the switching transients) is from dielectric absorbtion in parasitic capacitance - FR4 is no an especially good dielectric and has high DA. Capacitance from the input (pins 5,6,7,12 towards the +12V to -12 V step (pin 9) and maybe directly the integrator could be an issue. Ideally one would want some shields in between to reduce the capacitive coupling in the FR4.

[Zondar]

Most NU180 versions don't use the supply modulation, but they still need to connect the sense part somewhat with a short.

I'm curious: why do you say it should be connected? My boards have grounded Mod_sense1. However, looking at the associated circuitry, I don't see a reason why leaving it floating would be a problem.

By the way, connecting Mod_in to the switch selection pin (in modulation schemes) accomplishes nothing. Regardless of its voltage, either switch side A or B will be connected, without any control of the internal transmission gate's voltages by that pin being possible (metastability aside). It might as well be connected to ground.

Capacitance from the input (pins 5,6,7,12 towards the +12V to -12 V step (pin 9) and maybe directly the integrator could be an issue. Ideally one would want some shields in between to reduce the capacitive coupling in the FR4.

On my boards, 6 and 11 only are used for the 50k. The other pins associated with that resistor, 5, 7, 12 and 13, are not used and are floating. In retrospect, they could and probably should be grounded (except 13), though any decrease in capacitance on other nodes due to that would be negligible.

There are a few other pins that were left floating by default (out of paranoia) that could have and perhaps should have been grounded, if only on principle. For example, Pin 1, which in the genuine U180 is the chip's substrate connection, has no purpose in NU180. In the genuine U180, it looks like that's a virtual ground: it's floating with only a capacitor to ground. Instead, the substrate is probably biased internally, so it's no longer virtual. I think this should be grounded in future boards, and I'll review all pins like these again before making a new one.

[DB4UCH]

It is odd to see a difference between 10 PLC and the longer times. AFAIK the 3458 normally does the longer integration by averaging over multiple 10 PLC conversions. There is some way to get longer integration at a piece, but that mode is more noisy and rarely used.
I don't know if the averaging is done on A3 or only at the output side. There seems to be at least some extra delay when a 100 PLC conversion is complete. This could be some data transfer.
The delay alone could have some effect from some settling effect. However I see very little reason why the original U180 / NU180 would be much different in this aspect. This would also be 2 readings at essentially zero, but the transients from the precharge part and gate charge compensation can be slightly different.

The trend doesn't seem to hold when specifying the aperture and therefore integration time manually.
As for some timing: for a 10 NPLC conversion there is about 300µs between the AZ and measurement cycle. For 100NPLC there also are about 300µs between AZ and each respective reading part. The delay between the ten 10 NPLC parts of the 100 NPLC reading is about 400µs.
With front panel or ASCII GPIB operation there are about 20ms of delay between each reading block (for 1, 10 and 100 NPLCs) Using DINT and TRIG AUTO this delay gets reduced to <3ms.
The difference in zero point stays the same. So, if the effects are Hardware related, we are working on a timescale between 400µs to less than 3ms.

A point that can have some effect could be the data transfer via the fiber. This uses quite some current and may cause shifts in ground and the 5 V supply.

I also investigated this by removing U302 and L303 on the A3 board and JM101 on the A6 board, therefore disabling the cross guard fiberoptics completely. (I also disabled measurement complete via GPIB) I then bridged from Pin 1 and 8 at U302 (A3) to R106 / R107 on the A6 board therefore directly connecting the in- and outguard parts.
No difference in zero point or noise (the noise was even slightly worse) was observable, so I don't think that the fiberoptic drivers are the issue.

Greetings,
Simon

[hp3310a]

I'm reading along since this started and am very much admiring this great project. Who knows maybe I will own a 3458A in the future and no doubt it will be a drifty one given my budget.

Anyway, I didn't see it mentioned before and may this likely is a bad idea to address the VDD2/VDD fluctuations, but: What about adding suitably sized electrolytics to both supplies directly on the NU180 board? I have no idea if that would have detrimental effects on the rest of the A3 board or if that would load the circuit to much on the initial startup when they are discharged.

[Zondar]

So, while the zero point for 1 and 10 NPLCs is identical in my case, taking the measurements at 100 NPLCs shows that the zero point has shifted by somewhere between 0.5 to 1.2 µV in comparison to the 10 / 1 NPLC case.

I did a few short runs to look at this, measured on my long-term legacy board (pre-flip-flops, pull-downs on 80k's). Not a "good" ground, though.

Scale = Auto:

NPLC=1:     -3.226 uV
NPLC=10:   -3.256 uV
NPLC=100: -3.256 uV

So, 30 nV difference between NPLC=1 and NPLC=10 or 100.

Scale = 10V:

NPLC=1:     -2.378 uV
NPLC=10:   -3.079 uV
NPLC=100: -3.375 uV

So, about 0.7 uV difference between NPLC=1 and 10, a similar result to Simon's. I wish I had an idea or two about this. Perhaps the fact that it's worse on the 10V scale, or that the offset on NPLC=1 is different between Auto and 10V could be meaningful?

(HP3310A: We do have ceramic capacitors on the power pins, etc. We could always add more capacitance, and that's usually beneficial or at least harmless. Personally, I dislike the idea of electrolytics on it, though, and would prefer a few large ceramic ones or maybe tantalum.)

[DB4UCH]

So, about 0.7 uV difference between NPLC=1 and 10, a similar result to Simon's. I wish I had an idea or two about this. Perhaps the fact that it's worse on the 10V scale, or that the offset on NPLC=1 is different could be meaningful?

You need to calculate the result as PPM of Range, as it is a ADC or processing based artefact, the magnitude of the effect is then mostly range independent. (If you short the input at the ADC, it is fully independent of range)
So, your 30 nV would become something like 0.3PPM / range. Which is higher than one would expect, but you also have to take the frontend noise etc. into account.

But interestinly you have the offset switched (So primarily between 10 and 1 NPLC vs 100 and 10 NPLC), so you seem to have my early "fix" applied. (https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6140079/#msg6140079)
On my NU180 (FF based, v0.4.2), the difference between 1 an 10 NPLC is pretty much zero, while the 0.5-1µV offset exists between the 10 and 100NPLC range.

Greetings,
Simon

[Zondar]

You need to calculate the result as PPM of Range ...
So, your 30 nV would become something like 0.3PPM / range.

My brain refuses to think in terms other than Volts.

The quoted resolution on the 100 mV scale is 10 nV, but resolution only says so much. The accuracy is specified as 3 ppm of range, which is 300 nV. So leaving aside the offset for the moment*, the measured 30 nV difference isn't bad.

(* An offset at zero is virtually inevitable, and is typically subtracted mathematically, either internally (e.g. via a null button) or externally, though 3 uV feels a little high.)

Things are a little more difficult on the 10V scale. There, the accuracy is quoted as 0.05 ppm of scale, which is 0.5 uV. So 0.7-0.8 uV variation, which is under a factor of two away, isn't outrageously out of spec. 

Even with this problem, if my logic isn't wrong, a NU180-equipped machine might claim to be "8 digits", similar to where the slightly-elevated noise would put it. Does this make sense?

The problem feels solvable, and it should be quashed if at all possible. But one day we might have to be satisfied with something like an "8 digit" label, which would already be pretty awesome and something we should be proud of.

[DB4UCH]

The quoted resolution on the 100 mV scale is 10 nV, but resolution only says so much. The accuracy is specified as 3 ppm of range, which is 300 nV. So leaving aside the offset for the moment*, the measured 30 nV difference isn't bad.

(* An offset at zero is virtually inevitable, and is typically subtracted mathematically, either internally (e.g. via a null button) or externally, though 3 uV feels a little high.)

Things are a little more difficult on the 10V scale. There, the accuracy is quoted as 0.05 ppm of scale, which is 0.5 uV. So 0.7-0.8 uV variation, which is under a factor of two away, isn't outrageously out of spec. 

The LSB in the 100nV range is below 1nV for 10 / 100 NPLC at ~0.145nV @ 50Hz, although with the preamplifier noise etc., this resolution is of little to no use, so the 10nVs make more sense. The zero point itself is in spec, as +-1.06µV for 100mV / +-2.3µV are permissible for the 10V range (@Zondar you might want to run ACAL to correct the general offset from zero, then you should also be in spec)

For the 10V range, what you call accuracy (0.05 ppm) is the transfer accuracy, so comparing two voltages in the same range. If the NPLC isn't changed during the measurement, this effect doesn’t matter as it affects both voltages the same way.
Where it will have an impact is with the absolute accuracy, which is specified with 0.5PPM / 24h in the 10V range, it will likely still be in spec, tho.
Although if we look at the additional gain error graph from the datasheet, we also have some breathing room here.

In conclusion, I would say that this issue wouldn't negatively impact our goal to hit the original 3458As specs.

Even with this problem, if my logic isn't wrong, a NU180-equipped machine might claim to be "8 digits", similar to where the slightly-elevated noise would put it. Does this make sense?

I think we could definitively give the project an 8 digits rating, as even with our current elevated noise levels, we are about as noisy as a Keithley 2002 and following wanghars linearity measurements, also the linearity looks quite decent and is likely in spec.
The only thing that is still problematic is the TC, which at this point is poor, even for a bad 6.5-digit meter, although wanghars experiments with foil resistors have also shown great results in this regard.

I will play around a bit more with this zero issue, but even if we don't find the solution, I wouldn't consider it to be a dealbreaker.

Greetings,
Simon

[Zondar]

For the 10V range, what you call accuracy (0.05 ppm) is the transfer accuracy ... the absolute accuracy, which is specified with 0.5PPM / 24h in the 10V range, it will likely still be in spec, tho.

I think we could definitively give the project an 8 digits rating.

The only thing that is still problematic is the TC, which at this point is poor, even for a bad 6.5-digit meter, although wanghars experiments with foil resistors have also shown great results in this regard.

Specs can sometimes be ambiguous. I did mean "accuracy," presumably "absolute" (second table from top in DC section), not transfer accuracy. But both are 0.05 ppm of range anyway.

Also, one of us may be misconstruing the 24 hours condition. I took that to mean time since full calibration, not time since ACAL, etc. Otherwise, the 2 year spec is kind of silly.

Also, I see what appears to be an input offset spec of 5 uV for ranges 100 mV to 10V (page 21), which feels rather large, but would mean we are all within spec. I don't see 1.06 mV, etc. Did you perhaps calculate those numbers, and if so how?

I think it's the crew trying to make a modern A3 replacement that would really, really like a perfect 8.5 digits worth.

The reason I'm hanging on to my "legacy" board is that it's loaded with bulk foil resistors much like wanghar's. However, my crude attempt to measure TC failed, I think since I haven't worked on scripts to perform automated measurements of multiple parameters. I should make another attempt, but I'd also like to transfer the resistors to a newer board iteration.

[DB4UCH]

Specs can sometimes be ambiguous. I did mean "accuracy," presumably "absolute" (second table from top in DC section), not transfer accuracy. But both are 0.05 ppm of range anyway.

Also, one of us may be misconstruing the 24 hours condition. I took that to mean time since full calibration, not time since ACAL, etc. Otherwise, the 2 year spec is kind of silly.

Yes, it is the time after a full calibration and I interpreted the specs wrongly, so no 0.5 but 0.05 PPM of range is relevant here.

Also, I see what appears to be an input offset spec of 5 uV for ranges 100 mV to 10V (page 21), which feels rather large, but would mean we are all within spec. I don't see 1.06 mV, etc. Did you perhaps calculate those numbers, and if so how?

I took those numbers from the calibration manual, as those are the limits at which adjustment / repair is necessary.

[Kleinstein]

The offset that depends on the PLC setting may not be a direct problem for using the meter. I would more see it as a hint that something is not wroking as expected. The change in offset may well be only one consequence - the same issue could as well effect the INL. The offset change is relatively easy to measure compared to INL. So it would be nice to understand the off offset.
A point to test could be doing measurements to memory and this way get largely rid if the extra delay.
Another possible test would be individually triggered measurements with more delay and look if the delay makes a difference.
That the offset problem is smaller in the 100 mV / auto range suggests that the issue is after the gain (e.g. with the ADC) and not at the front with switching.

Having pins fully floating (that is not connected on the A3 board and the NU180) would be a bad. This could act as lossy capacitors. AFAIK there are not many such floating pins on the board (the CLIP shows pins 32,39,41 as NC for the board).

The Keitley 2002 noise is a bit hard to compare to. The keithley meters (2001,2002,2010,DMM7510) have extra low frequency noise that makes them really poor for some jobs, while OK for others. Form the reported noise the NU180 version would be comparable to the KS34470.

[Zondar]

The substrate pin (Pin 1) is the only "floating" pin, in quotes because it's actually a virtual ground. Nevertheless, I think it should be grounded in future boards.

By the way, if you only look at the boards, you will see a few unused pins that appear floating. Those are not actually floating because the A3 board connects to them. Pin 31, Mod_GND, is an example.

[DB4UCH]

A point to test could be doing measurements to memory and this way get largely rid if the extra delay.

Using the reading memory, I'm able to take individual 10 NPLC readings closer together than the 10x 10NPLC readings are taken for 100 NPLC.
The timing is now like this:
10 NPLC (memory: ~335µs between cycles for AZ and ~365µs between the readings) (without memory ~20ms between readings for ASCII)
100 NPLC (memory: ~335µs between cycles for AZ and ~435µs between the partial readings / and something close to this between the whole blocks) (without memory ~20ms between the blocks for ASCII)

Taking the readings with memory, the zero-point difference seems to invert (and even get worse?? Was mostly noise, it's now noisily around 0 difference. My script was only evaluating a single reading... Now the difference for the 10 to 100 NPLC case with memory is zero (the mean difference of multiple runs is less than 0.001 PPM). (without memory 100 NPLC was smaller than 10 NPLC, now it's larger)
So, the effects might be more on a <100µs timescale.

Greetings,
Simon

TBH. I'm not yet fully sold on my methology, so take those results with a grain of salt.

[DB4UCH]

I have now investigated this more and was able to find out that for 10xNPLC very close together no difference to 100NPLC remained.
I then used the timer function of the 3458A to shift the time between reading blocks (and verified that the shift actually works with an oscilloscope) and found a clear trend.
Above 1ms of delay between readings (DINT has about 2-3ms delay just for the GPIB) the zero point rapidly changes. This applies for 10 and 1 NPLC readings. With lower NPLC no obvious trend is observable.
I attached plots for 10 and 1 NPLC below. (The script I used shuffles through the different delays and repeats the measurement multiple times, as to keep the influence from drift to a minimum)
Quantitatively I think that this variance in timing can explain most of the difference in zero point.
As to what causes this effect, I don't know.

A second thing I observed was that the noise is also slightly dependent on the delay between readings (about 5% in the 1 NPLC case, 20% in the 0.1NPLC and something in between 10NPLC case.)
This could be caused by better rejection of the mains, so don't read too much into it yet. But it seems like the delay between the 10 NPLC blocks in a 100 NPLC reading might fall into one of those lower noise regions.
Don't take those noise results seriously yet, as I need to investigate further.

Greetings,
Simon

[Zondar]

Very interesting, Simon, and good input on the issue.

At first I thought it looked exponential with a knee of ~1 ms. But then I thought it might look more like a hockey stick: Two lines, one flat from zero to 1 ms, and then a line proceeding down.

If it's exponential, then I don't think anything on the board can cause it. The time constants are all way faster than that.

For the latter case (hockey-stick), the corner is about 1 ms, and beyond that you get:

Offset (ppm) ~= -0.05 * log10(period) + 0.06

However, the two conversions you made were fully independent, right? I would expect that the ADC is fully reset before each independent acquisition, to the point that they hopefully are truly independent.

I also noticed that the Cal sheet Simon posted allows for higher offsets and non-linearity as NPLC increases. It appears that what we are seeing is allowed for, or even expected. Is it only a question of degree? Do stock machines ever experience this?

[Kleinstein]

There can be long hidden time constant: one is from thermal effects. However with 2 essentially zero readings I would not expect much. There would be only the transient from AZ switching with the pre-charge step in between.
Another long time constant can come from dielectric absorbtion. This would especially be parasitic capacitors with some plastics. It would only be a little capacitance, but with poor dielectic quality. Dielectric absorption can be very slow.
A similar effect can happen with semi isolated islands the charge via leakage current. So this would be parasitic RC combinaiton with may be 1 pF and leakage resistance in the Tohms range.
I don't think this would be the case here, but a not working reset phase would also cause a delay dependent issue.

For the noise part the mains hum suppression depends on the delays, for the 10x10 PLC case. It should get better when the gaps in between add up to multiples of 20 ms. The way the small errors from not perfect mains frequency would be evenly spread out over 1 period.

[Zondar]

The plots are somewhat ambiguous, but to me it looks more like a power-law (logarithmic) effect than exponential. In that case, RC effects could be discounted. Plotting on a linear scale, or plotting derivatives, or fitting to both logarithmic and exponential curves might help conclude which it is.

Edit: Looking at the last 10 points or so in the first graph, the slope seems to be about -0.045 ppm / decade. The noise in that slope approximately matches the noise in the first n points, and are all within the same order of magnitude. This leads towards a power-law effect rather than an exponential (e.g. RC) effect.

If you extended the graph by another decade or two, and the slope still remained about the same, I'd say that would be fairly conclusive.

[DB4UCH]

If you extended the graph by another decade or two, and the slope still remained about the same, I'd say that would be fairly conclusive.

Here, I also tried fitting log and exp.
Greetings,
Simon

[Zondar]

The data for the extra ~2 decades you added appears to continue downward with the same slope as the prior decade or two does. Very tellingly, it continues downward past ~0.1s with no flattening as the exponential fit shows.

For the log fit, you included all data, including the clear plateau from 0 to somewhere around 2 ms. Excluding that, e.g. starting around 3 ms, the fit would be very good, and especially would fit far better than the exponential over the last decade, where the exponential fit begins to fail badly. Also, perhaps aside from Kleinstein's floating node hypothesis, there is no possibility of any time constants on the NU180 boards to reach anywhere near 0.127 seconds.

Here's what I think is happening: There is an intrinsic offset at zero time delay, which we have all seen. Past that, we see an additive noise floor transitioning into a time-dependent power-law drift mechanism. The knee we see in the chart is simply the point where the latter starts to exceed the former.

[Kleinstein]

The odd CPLD output drivers when in the high state without a pull up or pull down could also produce a long time constant when drifting from some 4 or 4.5 V up to near 5 V.