Phase noise measurement

[awallin]

6) Dual Mixer Time Difference: I don’t see any reason why the system couldn’t be used for DMTD as well. Using two incoming channels for DUT and reference, you would reduce the incoming noise using a 2nd channel for each.
....
 I would love to have help on this aspect of the project.

check this paper on arxiv: https://arxiv.org/abs/1605.03505 "Oscillator metrology with software defined radio"

we've also tried this with Ettus SDRs https://www.researchgate.net/publication/336825605_Software_Defined_Radio_Based_Phase_Meter_for_Frequency_Metrology

One issue with the Ettus SDRs is cross-talk between the ADC-channels.
If you make custom ADC-hardware this is where to focus. You probably want much more than 100 dB of isolation between the ADC-channels - as much as reasonably possible I guess...

[cncjerry]

Drum role please....  as in Nat Lampoon's Christmas Vacation...   there should be a drum role icon, no?

I have a plot!  oK, I roughed out the power supplies for the ADC board and Crystek oscillator.  I was just dying to get a plot out of this thing no matter what it looked like.

So I had on my desk an AD9912 DDS and also my crappy reference (in terms of noise) coming from my GPSDO.  Lots of reasons the plot is so bad, but it verifies that everything is working and that was my major concern.  I'm surprised the noise levels were this good to tell the truth.  Also, this is coming from the authors LivePlot exec, not the plotting code he wrote in Python.  That is why the X axis (frequency) scale isn't labeled correctly. 

The other thing I noticed was that the levels measured by the code were only up around 24% so that means I'm not getting the full dynamic range of the ADC.  But it is working and that is a small miracle for me in itself.

More to come.

Jerry

[cncjerry]

I haven't cleaned up the splitters, amp, etc but fired up my Cesium.  That has a decent oscillator in but nothing to write home about, or wait, am I not doing that now?

This is the Analog Devices AD9912 DDS set to 10Mhz and plotted for only 5 minutes or so.  This plot was made with the authors python code and includes both the real and imaginary Spectral Density.  I have to get a better understanding of the imaginary component and its relevance on this plot.  Also, these are not averaged after they are saved

So next steps are to clean up the ADC oscillator power;  Build the splitters and box it all up.  I have so much noise here from local FM stations it is really hard to do anything.  Three sides of my office are under ground so I get some protection but not enoug

I would say overall though, this was relatively easy to implement with optimistic results in the future.

Jerry

[RoGeorge]

Wow!   

[cncjerry]

For those that haven't been on Andrew's site, this plot shows some of the capability of his design.  The spurs around 1hz are related to a difference in the frequency between the DUT and reference of 1hz. He's using Wentzel ULN oscillators. He is also running much cleaner supplies than me.  My power supply parts and splitter boards should be here Monday.

Jerry

[cncjerry]

6) Dual Mixer Time Difference: I don’t see any reason why the system couldn’t be used for DMTD as well. Using two incoming channels for DUT and reference, you would reduce the incoming noise using a 2nd channel for each.
....
 I would love to have help on this aspect of the project.

check this paper on arxiv: https://arxiv.org/abs/1605.03505 "Oscillator metrology with software defined radio"

we've also tried this with Ettus SDRs https://www.researchgate.net/publication/336825605_Software_Defined_Radio_Based_Phase_Meter_for_Frequency_Metrology

One issue with the Ettus SDRs is cross-talk between the ADC-channels.
If you make custom ADC-hardware this is where to focus. You probably want much more than 100 dB of isolation between the ADC-channels - as much as reasonably possible I guess...

I just got around to looking at the papers linked above.  I wish that 2nd SDR paper had more detail.  I note that it is also using a Spartan 6 FPGA but it isn't written for reproduction.

[Ice-Tea]

Like so:

https://www.ebay.de/itm/HP-Agilent-11729C-Carrier-Noise-Test-Set/143510638931?hash=item2169e69153:g:sLgAAOSwg-VeKtlh

 

Yeah, my listing.

[cncjerry]

Like so:

https://www.ebay.de/itm/HP-Agilent-11729C-Carrier-Noise-Test-Set/143510638931?hash=item2169e69153:g:sLgAAOSwg-VeKtlh

 

Yeah, my listing.

I looked at the HP3048 as an option but also in reference to the analog mixing method and scrapped it for a number of reasons.  Mostly because i was told the software would need more work.  I thought I would be able to use my 3562a instead of the older 3561a and was talked out of that too.   I think that by the time I had the 3048a system running I would have a lot more money in it, but maybe not since I have the 3562a, 8568 and 8566 analyzers and I can write the code needed.  I would need the carrier noise test system like you are selling but for right now, the FPGA system seems to meet my needs.

[zs437442]

Reviving this topic as I am also getting ready to build Andrew's system, and have some questions for people who already built it.

A quick question:  I see in some pics that there is a wire from the FPGA board to the ADC board supplying the ADC power.  Where is this wire connected to on the FPGA board?  Perhaps somebody can share a close-up of this on their FPGA board.

Some other questions I have as I am reading more about this.  I was going to ask Andrew about these, but asking here first to see if I can get answers here instead of bothering Andrew:

Other Questions:
1) Andrew describes in his article (http://www.aholme.co.uk/PhaseNoise/Main.htm) that there are 6 decades of decimation and FFT length of about 1000 each.  However, looking at his code (LogFFT.cpp) I see 9 decades defined, with FFT lengths defined as const int FFT_LEN[DECADES] = {8192,8192,8192,1024,1024,1024,1024,1024,1024};  -  Why 9 decades in the code, and why the first 3 have the much higher FFT lengths?  There are 6 decades here with an FFT length of 1024 each, but I don't understand the need/purpose of the first 3 decades with 8192 lengths.

2) Andrew mentions in his article that the system noise floor is the imaginary part of the averaged cross correlation, whereas the real part shows the actual phase noise of the DUT.  Why the imaginary part is supposed to show the system noise floor? (Any references as to why this should be true will be appreciated.)  Googling cross correlation of two complex numbers didn't yield any obvious answers on this.


I have gone through all the posts here on this topic already.  Any other useful tips people have found that might be helpful for a new person for this system?

Thanks,

--zs

[suj]

...
A quick question:  I see in some pics that there is a wire from the FPGA board to the ADC board supplying the ADC power.  Where is this wire connected to on the FPGA board?  Perhaps somebody can share a close-up of this on their FPGA board.
...

Pin 6 of the J55 connector is VCC3V3. Pin 1 is marked with a small arrow.
Details:
SP605 Hardware User Guide, UG526 (v1.9) February 14, 2019, page 47.

[awallin]

2) Andrew mentions in his article that the system noise floor is the imaginary part of the averaged cross correlation, whereas the real part shows the actual phase noise of the DUT.  Why the imaginary part is supposed to show the system noise floor? (Any references as to why this should be true will be appreciated.)  Googling cross correlation of two complex numbers didn't yield any obvious answers on this.

See this review of the cross-spectrum technique https://arxiv.org/abs/1003.0113
"The cross-spectrum experimental method", Enrico Rubiola, Francois Vernotte

the basic cross-spectrum ideas in eqn. (10) and (11) are straightforward - for a long averaging time S_xy should converge to what we want to measure S_cc. Deriving that Im(S_xy) is the system noise floor requires studying that paper in some more detail - maybe with some numerical simulations for support..

[zs437442]

Thanks awallin.  That reference was very helpful.

Going through the paper ( https://arxiv.org/abs/1003.0113), I see that the eqn. 15 and 16 on page 16 is where the authors show the expansion of S_xy into real and imaginary parts, and it shows that DUT's "pure" contribution (C's) appear only in the real part. Thus, looks like the system noise gets equally distributed between the real and the imaginary parts of the cross correlation, and hence the imaginary part has half of the system noise, and hence is a good estimator of the system noise floor.  (This is my high level understanding.)

(BTW, I found what appears to be a typo in the paper on page 22, beginning of section 6.8, that says "It has been shown in Sec. 6 (Eq. (15)) that all the DUT signal goes into R{Syx}, and that R{Syx} contains only the instrument background."  Looks like authors meant to say I{Syx} for the instrument background.  If you agree, I might try to inform the authors about this.)

Regards,

[zs437442]

Suj,

You mentioned in one of yours posts that you used 125MHz differential sampling clock for the ADC as opposed to Andrew's 77MHz single-ended clock (since he found 125MHz was causing spurs for his 5MHz oscillator measurements due to harmonics interaction.)

Could you elaborate on the benefits you saw in using a 125MHz (is this because you want to be able increase your frequency coverage for the measurements?)  Any other benefits, like increased measurement sensitivity? 

Trying to see if we are able to quantify the benefits of using the differential clock, higher sampling rate and cleaner power supplies etc., over just using a simpler setup.  My plan was to just start with a simpler setup like what Andrew mentions in his "2021 update", using minicircuit splitters, no filters, no amps, and using two not so expensive reference oscillators...

Regards,

[cncjerry]

Here are some notes I was sending to bryman79 but his box was full.  He had asked about using another board, if you could test the code before committing to a board, the use of 80Mhz or 125Mhz instead of 77.76.  By the way, I didn't note below but the best ADC clock frequency is the one available up around 122.88 because of the extended harmonic relationship.  I've been trying to purchase one but they aren't available in small quantities.

1) code, instructions, etc are built around the 605 eval.  I don't know anyone that has tried to convert it to another board. 
2) A lot of the code actually runs in the PC, fully editable.  The FPGA is used for capture mostly.  All source is available.
3) Andrew's code that runs on the PC can be executed you just won't be able to load the FPGA or get any value from it, just a blank graph.
4) It is very important to minimize the harmonic relationship between the ADC clock, DUTs and references. So using a 77.76 produces a spur that is like the 59th harmonic of one of the clocks.  If you used an 80Mhz AdC clock, and measured a 10Mhz DUT, you would have a large spur at the multiples of 8hz.  You need to minimize the mathematical relationship between the ADC clock, the reference and the DUT because even the 59th harmonic can be seen at the levels we are hitting.

With dual references and the later setup using connectorized components, we are getting noise floors below -180dB.  If you get the setup running, send me your email as Andrew, Pawel, Adrian and I have a lot of threads on power supply grid noise reduction, use of dual refs, what splitters to use (we are back to non-resistive), anti-alias filters (Adrian is the brains of the outfit and he isn't running filters now).  Don't both with Andrews splitter/amps.  I built them before we knew better.  The splitters and filters are ok, but the choice of amp chip could have been better.

Adrian uses a different setup for his ADC clock but I don't know if it was proven to be worth it.  Andrew, Pawel and I use a small power supply with the LDO low noise regulator and a capacitive multiplier being fed in my case from a "lab grade" (right) Tektronix supply.  I finally used Dewalt 20V batteries into a 15V or appropriate regulator board for the test once I warmed everything up with a power supply.  This eliminated the power line (grid) noise and harmonics.  So plan to run the tests on batteries for everything.  Tests run up to 10hours with diminishing returns after an hour but worth the longer run.  The system performs far better than any DUT I have, many of which have very good PN below -170dB.

If you plan to use power supplies, build the circuit by Jim Williams in AN83 to test your supplies.  Adrian and I built one using an ssm2019 but I never got good results with that chip and the circuit in AN83 is well thought out.  Or just use batteries but you might find they inject a lot of noise (the rechargeables do).

You will need two low-noise references and I wouldn't bother with anything other than the Wenzel 501 series that have the datasheet available with PN below -165 at 10khz.  We have been scarfing them up on ebay like vultures for less than $70 shipped in the US.  You will then need to use shielded power runs with about 10,000uf right at the oscillators power pins, both the refs and DUTs.  You also have to isolate the system magnetically away from transformers, etc by at least a meter.  I ended up having some noise on my neutral wire that contributed to my decision to move to batteries.

Adding to the notes above, we ultimately got better results with two references, without filters, using non-resistive splitters on the DUT, with heavy capacitance all around, isolated from transformers.  We also found that amplifying the DUT and references and then bringing them down with high-quality fixed attenuators, or the variable Weischel(sic) attenuators, keeping the input above 95% as measured with Andrews code, produced the best results.  Adrian, who continues to be a very, very patient person, was helpful beyond any reasonable expectation.  He hit a noise flow below -180 but has very, very good references.

That's about all for now.  Let me know if you get the 605 board and build it out.  Very, very high-end results for very little money, comparatively.  I know people that spent 10x as much for nowhere near the results.

Jerry

[Gerhard_dk4xp]

I'd like to see Holme's machine spread over 2 RedPitayas.

https://www.redpitaya.com/

That would feature 2*2 ADCs, 2*2 DACs, 2 ZYNC FPGAs and
some ARMs including Linux, network and USB  for a reasonable price.
The 2 ADC groups could be arbitrarily separated.

But I have a timepod, so it is not probable that I do it.

Cheers,
 Gerhard

[RoV]

Hi cncjerry, I have discovered this thread only today  ...
I'd like to add my 1 cent to your initial doubt about poor estimated noise at low frequency using the delay line method. I haven't seen an explanation in the following posts, but I must admit I have looked at them quite rapidly.
The lower frequency that you can detect using a delayed version of the same oscillator depends on the amount of delay applied. You would need a huge delay of the order of 1 ms to get a solid estimate of PN at 1 kHz offset. This can be explained in math language, but is also easy to understand: the two versions that you are mixing must not be "artificially" correlated in the time window used for the estimate, which is at least T if you want a frequency resolution of 1/T. If delay is unsufficient, you get a delayed replica of the 1st signal inside the used part of the 2nd, so you have a degree of artificial correlation that impairs the result.
That means that it is quite complex to reach low frequency offsets with the delay method: one technique is e.g. with fiber optic delay lines (up to a few tens of us).

I have made a very simple experiment with two oscillators and an audio card several years ago. It is reported here: https://www.iw3ipd.microvise.it/xtal%20phase%20noise/xtal%20phase%20noise.htm. Sorry the text is in italian, but should be quite easy to automatically translate.

Bye,
Roberto

[cncjerry]

I'd like to see Holme's machine spread over 2 RedPitayas.

https://www.redpitaya.com/

That would feature 2*2 ADCs, 2*2 DACs, 2 ZYNC FPGAs and
some ARMs including Linux, network and USB  for a reasonable price.
The 2 ADC groups could be arbitrarily separated.

But I have a timepod, so it is not probable that I do it.

Cheers,
 Gerhard

I'm curious how much that would cost and the performance.  One issue is the ADC clock noise.  We use the LTC2175-14 14-Bit, 125Msps Low Power Quad ADCs on a DC1525 eval board with a low jitter crystek clock.   Power for the clock comes from low noise, LDO regulators with a cap multiplier. The RP looks like it uses the 2 channel version of the chip.  I don't know the math well enough to understand if the sampling delta between two boards would impact the cross correlation.

Cost for the equivalent parts would be around $1,000 for the DC1525 and the FPGA board but the FPGA could be cut significantly with another board as we are using the expensive eval version.  I think the RPs cost more than $500 per.  Once you have the adc and FPGA, then it is all about dual references,  power supplies (I use batteries now once the refs and dut are up to temp), splitter for the DUT and it's best to use amps and attenuators to maximize the adc bit depth.  Any electromagnetic radiation around it will show up.  Also the ref clock vs ADC clock has to be selected to minimize spurs.

Jerry

[cncjerry]

For those still kicking around building this system, it is running superbly using batteries for the reference power supply.  We also found that electromagnetic interference of any type from transformers across a room, can be detected spoiling a plot. Andrew has recently released a new version of his code though I haven't tested it, it is purported to cut the run time or produce much better results in the same time.

I finally found two q-bit qb-188 amps and when combined with a programmable attenuator, I'll be able to set the refs closer to full scale on the ADC input.  I spent a lot of time with low noise regulators but finally decided to use batteries, the 20v type for Dewalt power tools.  They have more than enough capacity for a run of many hours, are easy to charge, and simple spade lugs can be inserted for connections.

With the qbit amps and the rest of the setup, I am under my goal of producing a system for under $1,000 that compares favorably with the best commercial products at a much lower price point.

Jerry