Phase noise measurement

[cncjerry]

I first started looking at phase noise (PN) as it related to radio transmitters and receivers.  I somehow got sidetracked for a couple of years on the other side of oscillator performance, that being stability.  I think I am now well equipped to measure stability having several different systems and references including a Cs beam,  a number of rubidium units, three or four GPSDOs as well as interval counters, Dual mixer setups, counters, etc.  So now I am going back to PN measurement and I've found that it still looks like you have to spend a fortune to get a decent PN plot.

I've read about a dozen papers on the various PN measurement methods.  I tried KE5FXs PN.exe with my spectrum analyzers and even with my 8568 and the companion 85685 preselector/preamp, I can't get a noise floor low enough to characterize anything more than maybe a poorly performing DDS or other synthesizer.   I also am looking at the old HP 3048 system because that uses a readily available interface that I might be able to couple with my 3562a baseband FFT analyzer.  If I can't put that system together, then the HP 70K spectrum analyzer has a PN measurement module I remember so I'll have to dig in there again too.

But going back to the documents like that written by KE5FX as well as Keysight, it seems like I might be able to get down to around -140dB or so by using one of the quadrature measurement methods.   There are two outlined in the docs.  The first uses a reference brought in phase with the DUT and then phase shifted 90 degrees so that when mixed within a DBM, the amplitude noise and primary frequency can be eliminated so that by then low pass filtering and amplifying the remaining phase noise, it should be able to be plotted on a baseband analyzer.  You might be able to also detect the PN by using a sound card with a 384k sample rate and 24bit or more ADC.  The second quadrature method skips the reference and splits the DUT signal itself into two paths with the second path being delayed or brought into quadrature with possibly a twisted wire quadrature device like those discussed by Breed(?) and others.

So armed with both a twisted wire quadrature module and a delay line (for 10Mhz), I tried mixing a 10Mhz signal with itselft 90 degree shifted .  I got the 20Mhz output from the mixer as expected with the 10Mhz greatly reduced in amplitude but still detectable, possibly due to shielding and coupling from input to output.  I then ran this directly into the 3562a as it has a 100Khz filter on the front end just to see what I would get.  I saw some of the typical phase noise plot but nowhere near as pronounced as expected.  For instance, and I'll post a plot as this continues, I had maybe a curve from -120dB down to -135 or so, maybe -140dB, but I would have thought the frequencies closer to 1hz to have more amplitude. I thought about it later that maybe it had something to do with the input coupling on the 3562a and I'll look at that again tomorrow.

If anyone can point me in the right direction, I'd appreciate it.  If this is hopeless within a hobbyist budget, I'll accept that advice as well.

Thanks,

Jerry

edit: Links to some doc:
Keysight:

https://www.keysight.com/upload/cmc_upload/All/PhaseNoise_webcast_19Jul12.pdf

One of the more interesting:

https://www.npl.co.uk/special-pages/guides/gpg68_noise

John's paper:
http://www.ke5fx.com/phase_noise.pdf

This link sent to me via PM  is very interesting and I'm trying to get more info.  He realized the analog mixing and baseband conversion with a high performance ADC with great results down to -170dBc:

http://www.aholme.co.uk/PhaseNoise/Main.htm

This R&S paper is better than some but the issue is with spectrum analyzers is the high noise floor:
https://www.rohde-schwarz.com/us/applications/phase-noise-measurements-with-spectrum-analyzers-of-the-fse-family-application-note_56280-15577.html

The picture in this doc is what I am trying to realize in hardware.  The issue remains though, if you can boost the PN to a level that can be measured to -170dBc by a typical baseband analyzer:

https://www.analog.com/media/en/technical-documentation/application-notes/AN-0982.pdf

Site with a simple discussion of measuring phase using correlation:

https://www.edn.com/measure-phase-difference-using-correlation/

[Villain]

How much are you willing to spend? What carrier frequencies are we talking about?

[mawyatt]

Jerry,

We needed to measure PN of a newly developed over-moded acoustic wave resonator back ~1990, and didn't have the proper PN equipment (and no budget for such). Recall I was at the IEEE MTT conference where MaCom presented a paper utilizing two identical oscillators, which were mixed together resulting is a zero baseband since the oscillators would self inject lock to each other. The baseband residue is the PN from each like oscillator and can be amplified and displayed with a high resolution ADC or baseband analyzer.

We funded a grad student (ended up hiring him!) to build up a couple of these setups and wrapped two of the over-moded acoustic wave oscillators with towels for thermal isolation and powered by batteries, then a high gain low noise baseband amplifier followed. The PN measurements which were better than -140dBm at 1KHz offset for a ~2GHz oscillator about 5mm square, were impressive at the time. Later we confirmed these measurements with a proper HP PN instrument at another location.

Wish I could remember the MaCom paper, but my memory is fading  

Anyway, know this isn't exactly what you were looking for but maybe helps in your PN endeavors since it doesn't require any expensive specialized equipment.

Best,

Edit: MACOM paper courtesy of my colleague Alberto 

[RoGeorge]

There are many ways to measure and characterize the phase noise.  Would be nice to link or name the documents you were talking about.

Just for an approximation, to see which oscillator is worst, I once did like this:
- set a Rigol DS1054Z oscilloscope on the biggest memory depth
- look at the oscillator's waveform at a later moment, a second later or so after the trigger.

Because constant phase noise accumulates as a time jitter over time, the zero crossing observed a second later after the trigger will slightly differ with each trigger event.  This is an example made with pulses instead of sinusoidal waveforms, just to better illustrate the idea of phase noise leading to time jitter accumulation over time.  The later we look after triggering, the more the pulse jitter around the ideal time spot.  The peaks that never move are there just as a helping reference on the screen, they are not live signals.  The bigger the delay from the trigger, the more time jitter is observed.



That method is in fact limited by the stability and phase noise of the DS1054Z internal PLL, but good enough for a demo or to compare which oscillator has lower phase noise.

An instrument can be improvised on the spot with some very clean reference oscillator and a counter, then some software to read the measured time jitter and display the statistic of the results.

[SilverSolder]

[...] Because constant phase noise accumulates as a time jitter over time [...]

I don't understand this part -  Wouldn't the noise introduce both positive and negative jitter,  so it nets out to zero in the long run?

[RoGeorge]

Wouldn't the noise introduce both positive and negative jitter,  so it nets out to zero in the long run?

Yes, both negative and positive, and zero in average, yet it accumulates as larger and larger time jitter.  In fact, I re-"discovered" that myself, by accident, while trying to measure something else.  At first I was intrigued by the same question, until it was kindly explained in another forum by somebody named "cirip", whom I want to thank for.

The explanation had some math in it, but I'll try an intuitive one (as in rough and no math):
- phase noise can be seen as a frequency modulation (an ideal oscillator is FM modulate by some noise)
- frequency modulation can be seen as a "lenght" modulation (the length between two consecutive zero crossings)
- the noise has both + and - variations, averaging on zero

- let's make an analogy with a (foot) walking down an alley, where each wavelenght of the oscillator is a step made in the same direction, and the phase will be a small error, let's say randomly distributed in the range of +/- 0.1 steps
- we make one step, we arrive at the distance 1 +/- 0.1 steps
- if we walk 100 steps, we arrive in average at a distance of 100 steps, correct, but what will be the range of the final error?

The real question here is what is the worst possible error?  That would be if by chance all the errors (at each step) will be +0.1 (or -0.1).  In conclusion:
- walk 1 step and arrive at the distance 1 step +/- 0.1, so the end point is at [1 step +/-0.1] steps
- walk 10 steps and arrive at the distance 10 steps +/-0.1*10, so the end point is at [10 steps +/-1] steps
- ...
- walk 999 steps and arrive at the distance 999 steps +/-0.1*999, so the end point is at [999 steps +/-99.9] steps
- the more we walk, the bigger the range of the final error.

The +/- n steps is the error after walking n steps (caused by the noise), and this length error is what we perceive as time jitter on the oscilloscope.

[SilverSolder]

Wouldn't the noise introduce both positive and negative jitter,  so it nets out to zero in the long run?

Yes, both negative and positive, and zero in average, yet it accumulates as larger and larger time jitter.  At the first I was intrigued by the same question until it was kindly explained in another forum by somebody named "cirip".  In fact, I re-"discovered" that myself, by accident, while trying to measure something else.

The intuitive explanation (as in rough and no math) is like this:
- phase noise can be seen as a frequency modulation (an ideal oscillator is FM modulate by some noise)
- frequency modulation can be seen as a "lenght" modulation (the length between two consecutive zero crossings)
- the noise has both + and - variations, averaging on zero

- let's make an analogy with a (foot) walking down an alley, where each wavelenght of the oscillator is a step made in the same direction, and the phase will be a small error, let's say randomly distributed in the range of +/- 0.1 steps
- we make one step, we arrive at the distance 1 +/- 0.1 steps
- if we walk 100 steps, we arrive in average at a distance of 100 steps, correct, but what will be the range of the final error?

The real question here is what is the worst possible error?  That would be if by chance all the errors (at each step) will be +0.1 (or -0.1).  In conclusion:
- walk 1 step and arrive at the distance 1 step +/- 0.1, so the end point is at [1 step +/-0.1] steps
- walk 10 steps and arrive at the distance 10 steps +/-0.1*10, so the end point is at [10 steps +/-1] steps
- ...
- walk 999 steps and arrive at the distance 999 steps +/-0.1*999, so the end point is at [999 steps +/-99.9] steps
- the more we walk, the bigger the range of the final error.

The +/- n steps is the error after walking n steps (caused by the noise), and this length error is what we perceive as time jitter on the oscilloscope.

Thank you for the excellent explanation. 

So, are we in effect depending on the low frequency components of the phase noise to "stack up" and cause enough jitter to become visible?

[RoGeorge]

are we in effect depending on the low frequency components of the phase noise to "stack up" and cause enough jitter to become visible?

This is the next very good question, after the previous one.  Kind of yes, but there is yet another very tricky thing here.

Our (wrong) intuition would say:
- OK, so if I look n edges later from the triggering point (let's assume it's a square wave instead of sinus) I would see all the n'th falling edges uniformly distributed in the range of the final +/- error, around the average point, but this is not what we see!

Most of the edges are right near the expected average, even if the error came from a white noise.  So, initially all the values in the range were equally possible in the +/- error range, yet after many steps we see most of the errors will like to "cluster" around the average, only a very few fall farther away from the expected average.  The final errors distribution after many, many steps has a Gaussian shape.

This is because of something very fundamental to statistics, called Central Limit Theorem.  For our case it means that if we "accumulate" many errors equally distributed (white noise) we will end up with errors that are not equally distributed, the final errors will have a Gaussian distribution (Gaussian noise). 

The resulting Gaussian shape is very convenient for us, because we know that standard deviation \$\sigma\$ directly relates with the RMS power of the noise, while the mean value \$\mu\$ directly relates with the DC component of the noise.

That Gaussian shape happens no matter what when "adding randomness", and is sometimes called Normal Distribution.
https://en.wikipedia.org/wiki/Normal_distribution

Here's an interactive model of a Gaussian shape (in general), and how it changes with its standard deviation and its mean values \$\sigma\$ and \$\mu\$. (drag the sliders)
https://www.geogebra.org/classic/ehkwndma

[SilverSolder]

are we in effect depending on the low frequency components of the phase noise to "stack up" and cause enough jitter to become visible?

This is the next very good question, after the previous one.  Kind of yes, but there is yet another very tricky thing here.

Our (wrong) intuition would say:
- OK, so if I look n edges later from the triggering point (let's assume it's a square wave instead of sinus) I would see all the n'th falling edges uniformly distributed in the range of the final +/- error, around the average point, but this is not what we see!

Most of the edges are right near the expected average, even if the error came from a white noise.  So, initially all the values in the range were equally possible in the +/- error range, yet after many steps we see most of the errors will like to "cluster" around the average, only a very few fall farther away from the expected average.  The final errors distribution after many, many steps has a Gaussian shape.

This is because of something very fundamental to statistics, called Central Limit Theorem.  For our case it means that if we "accumulate" many errors equally distributed (white noise) we will end up with errors that are not equally distributed, the final errors will have a Gaussian distribution (Gaussian noise). 

The resulting Gaussian shape is very convenient for us, because we know that standard deviation \$\sigma\$ directly relates with the RMS power of the noise, while the mean value \$\mu\$ directly relates with the DC component of the noise.

That Gaussian shape happens no matter what when "adding randomness", and is sometimes called Normal Distribution.
https://en.wikipedia.org/wiki/Normal_distribution

Here's an interactive model of a Gaussian shape (in general), and how it changes with its standard deviation and its mean values \$\sigma\$ and \$\mu\$. (drag the sliders)
https://www.geogebra.org/classic/ehkwndma

Just testing my understanding....    as an example let's look at 100 edges 1 second apart...  we trigger on the first one, and look at how far edge no. 100 is away from the mathematically expected value of 100 seconds.   The distribution around the 100 second mark will be Gaussian if we do that - just like the error of each step along the way is also Gaussian.   Effectively, we end up amplifying the small Gaussian error of each step into something large enough that we can actually sample and measure - and from that we can work backwards to what the per-step error must be?

[mawyatt]

I would think the "scope method" would limit the range of measurement to something that has only moderately good PN since the measurement result is the root-sum-squared of the scope jitter and the DUT.

I don't think our moderately prices DSOs have really high quality low PN reference oscillators internally (they tend to be expensive) but if the DSO had an external reference input then one could supply a really low PN reference. Unfortunately my DSO doesn't have an external reference input 

Best,

[cncjerry]

How much are you willing to spend? What carrier frequencies are we talking about?

trying to keep it below $1k and I'm only looking at 10Mhz right now.

[TexasRanger]

I have little experience with high-frequency stuff, but I was recently fiddling around with some Jitter Cleaner for ADC Clocking, I figured that something like in the appended picture should work for high offset frequencys (>1kHz).

Jitter Cleaner ICs and EVMs for Jitter Cleaner ICs are quite cheap and low frequency offset phase noise should mainly be limited by the used VCXO.

[mawyatt]

There are many ways to measure and characterize the phase noise.  Would be nice to link or name the documents you were talking about.

My colleague supplied the IEEE MACOM Paper. See my edited post earlier.

Best

[cncjerry]

There are many ways to measure and characterize the phase noise.  Would be nice to link or name the documents you were talking about.

My colleague supplied the IEEE MACOM Paper. See my edited post earlier.

Best

Thanks, but correct me if I am wrong, but it looks like they are using the term "injection" for phase (e.g. injection locking v. phase locking) and if so, this is the procedure I'm currently evaluating.

I've been communicating via email with Andrew Holme and plan to build his system.  I'll post as i progress thru his FPGA based system and my analog version.

Thanks for all the comments.

Jerry

[mawyatt]

Thanks, but correct me if I am wrong, but it looks like they are using the term "injection" for phase (e.g. injection locking v. phase locking) and if so, this is the procedure I'm currently evaluating.

I've been communicating via email with Andrew Holme and plan to build his system.  I'll post as i progress thru his FPGA based system and my analog version.

Thanks for all the comments.

Jerry

Injection locking and phase locking are slightly different, check the Reference by Adler (7) at the end of the IEEE paper, also see figure 2 in the IEEE paper. Phase locking tends to attempt to keep the phase fixed whereas injection locking tends to keep the phase within a range.

Injection locking takes advantage of an oscillator's inherent non-linearity to "mix" with the injected signal and if the injected signal is within a frequency range called the locking range the oscillator will move frequency wise towards the injected signal. This works very similar to a PLL, but doesn't require the separate components of a PLL as the basic oscillator provides everything that's needed. We've used this concept many times for various applications, including one where a microwave receiver LO would injection lock to an incoming RF signal and demodulate the data for a very small single silicon chip direct downconversion receiver developed in ~1990 and later patented (5603111).

Best,

Edit:

This injection locking concept was first described by Van der Pol when he was experimenting with relaxation oscillators based upon neon bulbs.

[cncjerry]

I decided to build the system Andrew Holme built.  It is basically a DSP based version of what I'm still trying to do with with the phase shifted and mixed DUT, translated to baseband.  But even after filtering and amplifying the remaining phase noise after mixing, I'm still not getting the expected trace but getting closer.  I think I need more amplification.

So I ordered the sp605 board, the quad ADC, etc and plan to build Andrew's phase splitters.  He seems like a good guy and is providing a little help in addition to the basic layouts and the code.  It's amazing that he, as well as at least two others that built the system, are getting noise levels below -180dBc.

I'll post pictures as thing arrive.

Jerry

[mawyatt]

Just looked at Andrew's work, impressive indeed!!

Best,

[cncjerry]

With regards to power splitters, Andrew used his own design:

MCL PSC-2-2+  ---> pad -> 1Mhz Filter -> pad -> HMC580 AMP -> output to ch1
                       ---> pad -> 1Mhz Filter -> pad -> HMC580 AMP -> output to ch1

I'm going to build his splitter as I have the parts but after he had recommended I follow the path of one of the other builders and use connectorized parts from Minicircuits.  But instead I was thinking of just making a couple of changes to his design.  First, I would probably use some shielding between stages.  Then I was wondering about the PSC2-2.  Since most of my testing will be in either 5Mhz or 10Mhz, I can quickly design a Wilkinson Power Splitter for each frequency.  then even though I have the amp chip, it doesn't have the best noise figure so I was thinking of changing that out as well.  The HMC580 is obsolete anyway (I have 4 or 5 of them, need 4 for each frequency) but it had a NF over 4 and the new chip that is up to 4Ghz now, has an even higher NF.  There are a lot of LNAs that have lower NF but I have to look for one with the same footprint.  Ideas?

[mawyatt]

I would be concerned about any amplifiers placed in the DUT signal path, since all amplifiers are fundamentally mixers as they "mix" any 1/f, Power Supply or bias noise with the signal to some extent. So select an amp with very low 1/f noise as well as low NF, and pay close attention to the bias and power supply. This is why 30 years ago we went to the trouble of designing the baseband amplifier based upon a selected low 1/f noise npn differential pair as an input to a low 1/f noise op-amp, all powered by batteries.

Now you've pinged my interest in ultra-low phase noise measurements, like I need another topic of consideration 

Anyway, good luck with your phase noise endeavors and keep us posted on your progress.

Best,

[cncjerry]

Parts are beginning to arrive.  I have the ADC and ADC clock in-hand and the FPGA is out for delivery.  I'll post pictures a little later when I have time.

I sent Andrew a note today asking a few simple questions about his oscillators, but then added this:

6) Dual Mixer Time Difference: I don’t see any reason why the system couldn’t be used for DMTD as well. Using two incoming channels for DUT and reference, you would reduce the incoming noise using a 2nd channel for each. Then with the digitized DUT and Reference, mix them both with an NCO offset by 1hz or 10hz, low pass filter, zero crossing detect, and measure the ZCD delta from one channel (Ref x Offset) to the 2nd channel (DUT x offset).  You now have the delta that is scaled by 10e-6 for the 10hz offset and 10e-7 for the 1hz offset.  Moving the data to the PC, it would be plotted using TimeLab or Stable32 to produce Allan Deviation, Modified Allan deviation, etc charts.  So now your system is fully competitive with all the much more expensive alternatives.

So, now I have an extension to the project.  I've written a lot of DSP code but not on FGA but this shouldn't be all the complicated to implement.  I would love to have help on this aspect of the project.

[RoGeorge]

So, now I have an extension to the project.  I've written a lot of DSP code but not on FGA but this shouldn't be all the complicated to implement.  I would love to have help on this aspect of the project.

I would try to minimize any processing done on the FPGA side, and do as much processing as possible (if not all of the processing) in software, on the PC side.

If this is the first time working with FPGAs you'll have a surprise.  Verilog or VHDL (HDL = Hardware Description Language) are very different from being "yet another programming language".

HDL (Hardware Description Language) are not programming languages.  Think about HDL as a text file to describe a digital schematic.  HDL is not a programming language, does not describe an algorithm, HDL describes a schematic diagram.  For example, in a HDL source code there is no order of execution of the text lines, like it would be in a programming language.

Same with the HDL toolchain, very different from a compiler, and certainly not trivial to work with.

My point is:  forget about previous DSP implementations.  In fact, forget about any programming experience.  Nothing applies to FPGAs.  Programming knowledge will only add confusion when doing anything with a FPGAs, including DSP (unless you are using them with a HLS compiler, of course).  Not to say, depending on the FPGA manufacturer and the FPGA model, DSP IPs might not even be available in the toolchain without buying a very expensive license.

Sure, the math and the DSP theory still stands, but the rest of the implementation/optimization techniques, not so much.  OTOH, data acquisition and some local processing then streaming is somehow a standard application for an FPGA, so there might be some example FPGA projects out there with just the right hardware, as inspiration or to modify it. 

Anyway, not a weekend project (unless you have everything already written/developed), but rather a couple of months.

[cncjerry]

i'm not trying to minimize the FPGA effort but I should be able to use some of his code already to help me understand what is going on.  I've been doing a lot of reading already.

I'm attaching some of the pictures of parts arriving. Everyone loves pictures.  The only interesting one is the Crystek oscillator as I haven't seen that format before.  Basically you mount it to the ADC board and then inject 3.3V into the other end.  Andrew had made a very low noise power supply for his.  I plan to make a small PCB with the 3.3v regulator on it with a prominent SMA connector to allow it to attach directly to the back of the oscillator.

On the back of the ADC board is the connector compatible with that on the FPGA, name escapes me.  I'm going to look for an extension but I suspect it isn't avaiable.  Andrew cut the corner off his ADC board to allow it to clear an SFP cage on the FPGA when mounted. Others decided to remove the SFP cage as it wasn't being used.

The FPGA is due to be here today as well.

Getting back to the power splitter, it surprised me to see the pad->filter->pad->amp path as why reduce a signal that is already very low.  So I'm going to think about that more and probably just use connectorized modules and if I don't get as-good results, then go back and build his splitters.

More to come.

Jerry

[cncjerry]

3rd try, having a hard time posting.  Attachments are failing security checks...

quick update, the SP605 board arrived Friday and man did it take some screwing around on an old XP laptop (recommended) go get the xilinx code downloaded and installed.  Once I got it installed I had some problems getting the author's code to work but it was all settings that I somehow screwed up even though his notes were clear.  Ha, doesn't surprise me at all.  Once I had his code loading the FPGA, I was able to get the ethernet to bind so I would say I am just about done with that end of the setup.  I have all the parts for the splitters but still looking at connectorized options.

I sent the author Bill Riley's paper on DMTD and he is looking to see if that can be easily implemented on the same board.  To me that code looks simpler.

I now have to find a decent reference 10Mhz oscillator. The HP 10811 in my Cesium beam has measured well in the past but I need something much better.  The author uses a Wentzel Ultra Low Noise at 5Mhz for his 5Mhz testing.  So I'm going to start looking harder at references.

Note how the ADC card overlaps the SFP cage.  The author had trimmed the corner of the ADC card and others removed the SFP cage.  I was looking for a small FMC-LPC riser but man, was that expensive.  If anyone has other ideas please let me know.  I'm not sure if the ADC wont just press down into the FMC connector enough or not.  It seems to have sufficient contact.  The author had checked the gerbers before trimming the ADC card corner.  I think getting that SFP cage off that board will be tough and not worth the risk even though I have a solder sucker setup.  So I'll probably trim the ADC PCB corner off.

More to come.

Jerry

[suj]

Great to see this topic! I'm also in the process of building this PN analyzer. My intention is to build all parts into a common box and shield them thoroughly. I decided to cut the SFP cage, this FPGA board will only be used for this analyzer. I have already designed the housing for the ADC board using layers of water-jet or laser cut aluminum sheet. I have used such housings before and they give good results. I also designed a clock board, I decided to use a 125 MHz clock in the differential version. The ADC board has two clock inputs and you can change the configuration to differential. As a clock generator I used a Crystek CCHD-945X-25-125 next LMK1C1102 driver, then an external LC filter (as described in the Linear/AD datasheet) and finally the LTC6957-1. I also adapted the clock board to a housing similar to the ADC board. I'm in the process of designing my own version of the splitter, I decided to use Mini Circuits GALI-4 + amplifiers, I have the results of residual phase noise measurements for them. It remains for me to design a universal power supply for reference generators (low-noise +5/12/15 V power supply) and put everything together.

[cncjerry]

Suj, cool, I'll send a PM so we can talk via email. 

You might note from my userid that I have lots of CNC gear and plan to make a nice case for this unit.  I have a box that came from some recent expensive telecom gear that I picked up on eBay for $25.  It is really nice and was built using that extruded aluminum typically used for robotics and some CNC router tables, can't remember what it is called.  It also had two high quality switching power supplies but I plan to use this toroid transformer I've had and build my own from the wall on thru.

Andrew has really been helpful.  When I couldn't get the FPGA stream to load with a JTAG error he sent me a custom version of his Liveplot that wrote a log that diagnosed the problem in minutes.  I have it running on ISE 14.7 under win10 as he suggested in his doc.  One other thing, once you have the FPGA loaded you can check the incoming levels and he recommended the ADCs be driven at 95% of peak. 

I looked at the differential clock and with that Crystek sitting right on top of the ADC board with the SMA connector, I couldn't imagine adding any more parts would help.  I would think the differential clock would be helpful if the clock cable runs were long but am going to try what Andrew did first.

Andrew and I traded emails on the power supplies.  He used an LDO with a capacitance multiplier for the Crystek.  I am going to use a cap multiplier followed by either an LT3042 or LT3045 LDO. I see you used the 3045.  There was a paper someone sent me on LDO and noise that stated they had lower noise without a cap in front of it.  The 3042 and 3045 have ridiculously low noise, less than 1uV with very high PSRR.  Since they are good for up to 500ma (3045) or 200ma (3042) at up to 20V, I will probably drive the ADC clock, ADC board and splitter amps with them.

The amp he used in the splitter is obsolete but there is a 4Gig version.  Both have relatively high noise figures at over 4dB and the new at 4.2dB IIRC.  There are a lot of other amps in MMIC format that are 3dB or below.  AT 5Mhz and 10Mhz those simple dual JFET push-pull amps have noise figures below 3.  These NewWave amps supposedly have NF of 1.18 at 50Mhz and I'm going to see if they have one from 5Mhz to 10Mhz.

Lastly, the FPGA communicates with the PC app through a dedicated 1gigE ethernet cable using TCPIP streams.  It would be possible to open another stream within the PC to talk to Timelab but I don't know if it is necessary since all you really need is the phase plot and his simple python script does a find job.

I wish you luck, please post some plots.  Love your cables.  I have to get some better ones for this project.

Jerry

[awallin]

6) Dual Mixer Time Difference: I don’t see any reason why the system couldn’t be used for DMTD as well. Using two incoming channels for DUT and reference, you would reduce the incoming noise using a 2nd channel for each.
....
 I would love to have help on this aspect of the project.

check this paper on arxiv: https://arxiv.org/abs/1605.03505 "Oscillator metrology with software defined radio"

we've also tried this with Ettus SDRs https://www.researchgate.net/publication/336825605_Software_Defined_Radio_Based_Phase_Meter_for_Frequency_Metrology

One issue with the Ettus SDRs is cross-talk between the ADC-channels.
If you make custom ADC-hardware this is where to focus. You probably want much more than 100 dB of isolation between the ADC-channels - as much as reasonably possible I guess...

[cncjerry]

Drum role please....  as in Nat Lampoon's Christmas Vacation...   there should be a drum role icon, no?

I have a plot!  oK, I roughed out the power supplies for the ADC board and Crystek oscillator.  I was just dying to get a plot out of this thing no matter what it looked like.

So I had on my desk an AD9912 DDS and also my crappy reference (in terms of noise) coming from my GPSDO.  Lots of reasons the plot is so bad, but it verifies that everything is working and that was my major concern.  I'm surprised the noise levels were this good to tell the truth.  Also, this is coming from the authors LivePlot exec, not the plotting code he wrote in Python.  That is why the X axis (frequency) scale isn't labeled correctly. 

The other thing I noticed was that the levels measured by the code were only up around 24% so that means I'm not getting the full dynamic range of the ADC.  But it is working and that is a small miracle for me in itself.

More to come.

Jerry

[cncjerry]

I haven't cleaned up the splitters, amp, etc but fired up my Cesium.  That has a decent oscillator in but nothing to write home about, or wait, am I not doing that now?

This is the Analog Devices AD9912 DDS set to 10Mhz and plotted for only 5 minutes or so.  This plot was made with the authors python code and includes both the real and imaginary Spectral Density.  I have to get a better understanding of the imaginary component and its relevance on this plot.  Also, these are not averaged after they are saved

So next steps are to clean up the ADC oscillator power;  Build the splitters and box it all up.  I have so much noise here from local FM stations it is really hard to do anything.  Three sides of my office are under ground so I get some protection but not enoug

I would say overall though, this was relatively easy to implement with optimistic results in the future.

Jerry

[RoGeorge]

Wow!   

[cncjerry]

For those that haven't been on Andrew's site, this plot shows some of the capability of his design.  The spurs around 1hz are related to a difference in the frequency between the DUT and reference of 1hz. He's using Wentzel ULN oscillators. He is also running much cleaner supplies than me.  My power supply parts and splitter boards should be here Monday.

Jerry

[cncjerry]

6) Dual Mixer Time Difference: I don’t see any reason why the system couldn’t be used for DMTD as well. Using two incoming channels for DUT and reference, you would reduce the incoming noise using a 2nd channel for each.
....
 I would love to have help on this aspect of the project.

check this paper on arxiv: https://arxiv.org/abs/1605.03505 "Oscillator metrology with software defined radio"

we've also tried this with Ettus SDRs https://www.researchgate.net/publication/336825605_Software_Defined_Radio_Based_Phase_Meter_for_Frequency_Metrology

One issue with the Ettus SDRs is cross-talk between the ADC-channels.
If you make custom ADC-hardware this is where to focus. You probably want much more than 100 dB of isolation between the ADC-channels - as much as reasonably possible I guess...

I just got around to looking at the papers linked above.  I wish that 2nd SDR paper had more detail.  I note that it is also using a Spartan 6 FPGA but it isn't written for reproduction.

[Ice-Tea]

Like so:

https://www.ebay.de/itm/HP-Agilent-11729C-Carrier-Noise-Test-Set/143510638931?hash=item2169e69153:g:sLgAAOSwg-VeKtlh

 

Yeah, my listing.

[cncjerry]

Like so:

https://www.ebay.de/itm/HP-Agilent-11729C-Carrier-Noise-Test-Set/143510638931?hash=item2169e69153:g:sLgAAOSwg-VeKtlh

 

Yeah, my listing.

I looked at the HP3048 as an option but also in reference to the analog mixing method and scrapped it for a number of reasons.  Mostly because i was told the software would need more work.  I thought I would be able to use my 3562a instead of the older 3561a and was talked out of that too.   I think that by the time I had the 3048a system running I would have a lot more money in it, but maybe not since I have the 3562a, 8568 and 8566 analyzers and I can write the code needed.  I would need the carrier noise test system like you are selling but for right now, the FPGA system seems to meet my needs.

[zs437442]

Reviving this topic as I am also getting ready to build Andrew's system, and have some questions for people who already built it.

A quick question:  I see in some pics that there is a wire from the FPGA board to the ADC board supplying the ADC power.  Where is this wire connected to on the FPGA board?  Perhaps somebody can share a close-up of this on their FPGA board.

Some other questions I have as I am reading more about this.  I was going to ask Andrew about these, but asking here first to see if I can get answers here instead of bothering Andrew:

Other Questions:
1) Andrew describes in his article (http://www.aholme.co.uk/PhaseNoise/Main.htm) that there are 6 decades of decimation and FFT length of about 1000 each.  However, looking at his code (LogFFT.cpp) I see 9 decades defined, with FFT lengths defined as const int FFT_LEN[DECADES] = {8192,8192,8192,1024,1024,1024,1024,1024,1024};  -  Why 9 decades in the code, and why the first 3 have the much higher FFT lengths?  There are 6 decades here with an FFT length of 1024 each, but I don't understand the need/purpose of the first 3 decades with 8192 lengths.

2) Andrew mentions in his article that the system noise floor is the imaginary part of the averaged cross correlation, whereas the real part shows the actual phase noise of the DUT.  Why the imaginary part is supposed to show the system noise floor? (Any references as to why this should be true will be appreciated.)  Googling cross correlation of two complex numbers didn't yield any obvious answers on this.


I have gone through all the posts here on this topic already.  Any other useful tips people have found that might be helpful for a new person for this system?

Thanks,

--zs

[suj]

...
A quick question:  I see in some pics that there is a wire from the FPGA board to the ADC board supplying the ADC power.  Where is this wire connected to on the FPGA board?  Perhaps somebody can share a close-up of this on their FPGA board.
...

Pin 6 of the J55 connector is VCC3V3. Pin 1 is marked with a small arrow.
Details:
SP605 Hardware User Guide, UG526 (v1.9) February 14, 2019, page 47.

[awallin]

2) Andrew mentions in his article that the system noise floor is the imaginary part of the averaged cross correlation, whereas the real part shows the actual phase noise of the DUT.  Why the imaginary part is supposed to show the system noise floor? (Any references as to why this should be true will be appreciated.)  Googling cross correlation of two complex numbers didn't yield any obvious answers on this.

See this review of the cross-spectrum technique https://arxiv.org/abs/1003.0113
"The cross-spectrum experimental method", Enrico Rubiola, Francois Vernotte

the basic cross-spectrum ideas in eqn. (10) and (11) are straightforward - for a long averaging time S_xy should converge to what we want to measure S_cc. Deriving that Im(S_xy) is the system noise floor requires studying that paper in some more detail - maybe with some numerical simulations for support..

[zs437442]

Thanks awallin.  That reference was very helpful.

Going through the paper ( https://arxiv.org/abs/1003.0113), I see that the eqn. 15 and 16 on page 16 is where the authors show the expansion of S_xy into real and imaginary parts, and it shows that DUT's "pure" contribution (C's) appear only in the real part. Thus, looks like the system noise gets equally distributed between the real and the imaginary parts of the cross correlation, and hence the imaginary part has half of the system noise, and hence is a good estimator of the system noise floor.  (This is my high level understanding.)

(BTW, I found what appears to be a typo in the paper on page 22, beginning of section 6.8, that says "It has been shown in Sec. 6 (Eq. (15)) that all the DUT signal goes into R{Syx}, and that R{Syx} contains only the instrument background."  Looks like authors meant to say I{Syx} for the instrument background.  If you agree, I might try to inform the authors about this.)

Regards,

[zs437442]

Suj,

You mentioned in one of yours posts that you used 125MHz differential sampling clock for the ADC as opposed to Andrew's 77MHz single-ended clock (since he found 125MHz was causing spurs for his 5MHz oscillator measurements due to harmonics interaction.)

Could you elaborate on the benefits you saw in using a 125MHz (is this because you want to be able increase your frequency coverage for the measurements?)  Any other benefits, like increased measurement sensitivity? 

Trying to see if we are able to quantify the benefits of using the differential clock, higher sampling rate and cleaner power supplies etc., over just using a simpler setup.  My plan was to just start with a simpler setup like what Andrew mentions in his "2021 update", using minicircuit splitters, no filters, no amps, and using two not so expensive reference oscillators...

Regards,

[cncjerry]

Here are some notes I was sending to bryman79 but his box was full.  He had asked about using another board, if you could test the code before committing to a board, the use of 80Mhz or 125Mhz instead of 77.76.  By the way, I didn't note below but the best ADC clock frequency is the one available up around 122.88 because of the extended harmonic relationship.  I've been trying to purchase one but they aren't available in small quantities.

1) code, instructions, etc are built around the 605 eval.  I don't know anyone that has tried to convert it to another board. 
2) A lot of the code actually runs in the PC, fully editable.  The FPGA is used for capture mostly.  All source is available.
3) Andrew's code that runs on the PC can be executed you just won't be able to load the FPGA or get any value from it, just a blank graph.
4) It is very important to minimize the harmonic relationship between the ADC clock, DUTs and references. So using a 77.76 produces a spur that is like the 59th harmonic of one of the clocks.  If you used an 80Mhz AdC clock, and measured a 10Mhz DUT, you would have a large spur at the multiples of 8hz.  You need to minimize the mathematical relationship between the ADC clock, the reference and the DUT because even the 59th harmonic can be seen at the levels we are hitting.

With dual references and the later setup using connectorized components, we are getting noise floors below -180dB.  If you get the setup running, send me your email as Andrew, Pawel, Adrian and I have a lot of threads on power supply grid noise reduction, use of dual refs, what splitters to use (we are back to non-resistive), anti-alias filters (Adrian is the brains of the outfit and he isn't running filters now).  Don't both with Andrews splitter/amps.  I built them before we knew better.  The splitters and filters are ok, but the choice of amp chip could have been better.

Adrian uses a different setup for his ADC clock but I don't know if it was proven to be worth it.  Andrew, Pawel and I use a small power supply with the LDO low noise regulator and a capacitive multiplier being fed in my case from a "lab grade" (right) Tektronix supply.  I finally used Dewalt 20V batteries into a 15V or appropriate regulator board for the test once I warmed everything up with a power supply.  This eliminated the power line (grid) noise and harmonics.  So plan to run the tests on batteries for everything.  Tests run up to 10hours with diminishing returns after an hour but worth the longer run.  The system performs far better than any DUT I have, many of which have very good PN below -170dB.

If you plan to use power supplies, build the circuit by Jim Williams in AN83 to test your supplies.  Adrian and I built one using an ssm2019 but I never got good results with that chip and the circuit in AN83 is well thought out.  Or just use batteries but you might find they inject a lot of noise (the rechargeables do).

You will need two low-noise references and I wouldn't bother with anything other than the Wenzel 501 series that have the datasheet available with PN below -165 at 10khz.  We have been scarfing them up on ebay like vultures for less than $70 shipped in the US.  You will then need to use shielded power runs with about 10,000uf right at the oscillators power pins, both the refs and DUTs.  You also have to isolate the system magnetically away from transformers, etc by at least a meter.  I ended up having some noise on my neutral wire that contributed to my decision to move to batteries.

Adding to the notes above, we ultimately got better results with two references, without filters, using non-resistive splitters on the DUT, with heavy capacitance all around, isolated from transformers.  We also found that amplifying the DUT and references and then bringing them down with high-quality fixed attenuators, or the variable Weischel(sic) attenuators, keeping the input above 95% as measured with Andrews code, produced the best results.  Adrian, who continues to be a very, very patient person, was helpful beyond any reasonable expectation.  He hit a noise flow below -180 but has very, very good references.

That's about all for now.  Let me know if you get the 605 board and build it out.  Very, very high-end results for very little money, comparatively.  I know people that spent 10x as much for nowhere near the results.

Jerry

[Gerhard_dk4xp]

I'd like to see Holme's machine spread over 2 RedPitayas.

https://www.redpitaya.com/

That would feature 2*2 ADCs, 2*2 DACs, 2 ZYNC FPGAs and
some ARMs including Linux, network and USB  for a reasonable price.
The 2 ADC groups could be arbitrarily separated.

But I have a timepod, so it is not probable that I do it.

Cheers,
 Gerhard

[RoV]

Hi cncjerry, I have discovered this thread only today  ...
I'd like to add my 1 cent to your initial doubt about poor estimated noise at low frequency using the delay line method. I haven't seen an explanation in the following posts, but I must admit I have looked at them quite rapidly.
The lower frequency that you can detect using a delayed version of the same oscillator depends on the amount of delay applied. You would need a huge delay of the order of 1 ms to get a solid estimate of PN at 1 kHz offset. This can be explained in math language, but is also easy to understand: the two versions that you are mixing must not be "artificially" correlated in the time window used for the estimate, which is at least T if you want a frequency resolution of 1/T. If delay is unsufficient, you get a delayed replica of the 1st signal inside the used part of the 2nd, so you have a degree of artificial correlation that impairs the result.
That means that it is quite complex to reach low frequency offsets with the delay method: one technique is e.g. with fiber optic delay lines (up to a few tens of us).

I have made a very simple experiment with two oscillators and an audio card several years ago. It is reported here: https://www.iw3ipd.microvise.it/xtal%20phase%20noise/xtal%20phase%20noise.htm. Sorry the text is in italian, but should be quite easy to automatically translate.

Bye,
Roberto

[cncjerry]

I'd like to see Holme's machine spread over 2 RedPitayas.

https://www.redpitaya.com/

That would feature 2*2 ADCs, 2*2 DACs, 2 ZYNC FPGAs and
some ARMs including Linux, network and USB  for a reasonable price.
The 2 ADC groups could be arbitrarily separated.

But I have a timepod, so it is not probable that I do it.

Cheers,
 Gerhard

I'm curious how much that would cost and the performance.  One issue is the ADC clock noise.  We use the LTC2175-14 14-Bit, 125Msps Low Power Quad ADCs on a DC1525 eval board with a low jitter crystek clock.   Power for the clock comes from low noise, LDO regulators with a cap multiplier. The RP looks like it uses the 2 channel version of the chip.  I don't know the math well enough to understand if the sampling delta between two boards would impact the cross correlation.

Cost for the equivalent parts would be around $1,000 for the DC1525 and the FPGA board but the FPGA could be cut significantly with another board as we are using the expensive eval version.  I think the RPs cost more than $500 per.  Once you have the adc and FPGA, then it is all about dual references,  power supplies (I use batteries now once the refs and dut are up to temp), splitter for the DUT and it's best to use amps and attenuators to maximize the adc bit depth.  Any electromagnetic radiation around it will show up.  Also the ref clock vs ADC clock has to be selected to minimize spurs.

Jerry

[cncjerry]

For those still kicking around building this system, it is running superbly using batteries for the reference power supply.  We also found that electromagnetic interference of any type from transformers across a room, can be detected spoiling a plot. Andrew has recently released a new version of his code though I haven't tested it, it is purported to cut the run time or produce much better results in the same time.

I finally found two q-bit qb-188 amps and when combined with a programmable attenuator, I'll be able to set the refs closer to full scale on the ADC input.  I spent a lot of time with low noise regulators but finally decided to use batteries, the 20v type for Dewalt power tools.  They have more than enough capacity for a run of many hours, are easy to charge, and simple spade lugs can be inserted for connections.

With the qbit amps and the rest of the setup, I am under my goal of producing a system for under $1,000 that compares favorably with the best commercial products at a much lower price point.

Jerry