Electronics > Metrology

Prema 6048 teardown

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Thanks, that patent of 2001 used the term "best-fit line" instead of "linear regression" but it shows the idea. Interesting enough they considered the method a good substitute to the multislope method like used in the Advantest R6581 with several different current sources, meant to solve the same problem at end of run-down.

Of course, if one can do it with a MCU and its built-in ADC, that's interesting. I thought a MCU built-in ADC might be to noisy and to produce more jitter. Maybe it just needs a slope amplfier (same as comparator). And it depends on how ADC sampling/trigger reacts to the 3.6864 MHz PWM time base. The LTC part is near ideal in that respect (psec aperture jitter).

Regards, Dieter

Best fit line and linear regression is the same, just different words.
The idea with an ADC to measure the charge is also used in the HP multislope 3 and 4, just with a much faster modulation. In case of the MS3 the modulation is with rather large blocks and thus a large range covered by the auxiliary ADC. AFAIK the MS4 ADC uses a more PWM like feedback and thus a much smaller residual charge.  The MS3 and very likely (because of the patent) also the MS4 uses a single ADC reading and than a slow measured up front. The linear regression is kind of a way to average over more readings and repeat the the scale factor calibration for every zero crossing.

The ADC should still be relatively fast, so that one can get a decent number of readings in the time. However I don't see a real need for very high resolution. The point is getting a little more resolution, like maybe some extra 4 or 6 bits. So enough to get an effective time resolution in the 5-10 ns range. Within limits one can trade resolution for speed. A µC internal ADC may be a bit on the slow side. Some 10 bits at 5 MSPS would ideally resolve the 200 ns in 500-1000 parts. To get a bit more averaging and less noise bandwidth one would however loose some of the resolution. It may still be good enough.
The main point of the prema ADC are using reference switching with drive and sense switches. This can be precise with no effect of the switch resistance, but it still adds a bit switching error and needs relatively long settling time. So this requires the relatively slow modulation and large integrator capacitor.
Another point with the 6048 is the ADC for only 1 polarity with the reference path switching on / off and not both polarities. This leads to a noise that depends on the input voltage. So with 0 input the ADC can be quite low noise, but with high voltage there can be quite some extra noise. A bit like adding much of the ADC noise to the reference side and not to the input.

The simple direct feedback control with the comparator works OK with the rather strong reference (1.4 mA for the 6048), which is not ideal noise wise.  My understanding / guess that the MS4 ADC uses the 2nd auxiliary ADC for the Feedback control to get away with a weaker reference. The solartron DMMs use the extra forcing signal to support the feedback. Otherwise they are quite similar.

I am not so sure how much it would help, but a possible way to improve on the noise would be some filtering the reference. The LTZ1000 is low noise but still relatively high noise compared to OP-amps. The reference is only used for relatively short (less than 30% duty cycle) pulses and this increses the BW for the reference side. So ref. noise in the 100 Hz + harmonics bands can have an effect. Filtering could reduce this higher frequency noise contribution.

Mickle T.:

--- Quote from: Kleinstein on July 07, 2023, 07:57:59 pm ---The solartron DMMs use the extra forcing signal to support the feedback. Otherwise they are quite similar.
--- End quote ---
Prema is known to have several proprietary types of pulse feedback ADCs, including those with a convergence acceleration signal (US5066955).
Thaler uses the same topology as in the early Prema patents (1973, 1982).

As far as i understand one can improve timing resolution at the end of run-down by using a TDC-like circuit to measure the timing of the comparator relative to the integrator timebase. The TDC involves another integrator for a reference current during the delay so one can later digitize the delay with good resolution, to get a fractional, sub cycle time measurement.

Regards, Dieter

With a different control hardware one would not be limited to the rather low 3.6x MHz clock for the timing. Just a higher clock for the PLL may be enough for a little more timing resolution. There is anyway the noise limit for the comparator. Due to the relatively large capacitor and thus moderately slow slope the noise could well be limiting:
In the 6048 this is 1.4 mA/0.5 µF = 2.8 mV/ µs , which is more comparable to the slow slopes in a normal MS ADC. The noise voltage is given by the integrator ( ~ 10 nV/sqrt(Hz)) and if added slope amplifier with about a comparable noise. The BW is set by the comparator or ideally the slope amplifier. To get reasonble fast response for short pulses one would likely need 100 kHz or a bit more. So one can expect a noise voltage of some 4.4 µV or a timing noise of some 1.6 ns  (more with a high BW).

With the long integration time one would likely not need that much resolution anyway.


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