Prema BK7 derived meter

[dietert1]

While studying the Prema 6048 and its BK7 microcircuit, we discovered some shortcomings and i want to study a little how one can improve. One of the weaker points was the timebase of the time division ADC implemented in the BK7 microcircuit. The Prema meters use a HC4046 VCO (RC relaxation oscillator) with a PLL. So there will be some phase noise and variable frequency. How to use a crystal oscillator instead? First i made a log of our 50 Hz mains frequency using a HP5335 meter. Gate aperture of the HP5335 is 0.5 sec. A crystal cannot be tuned enough in order to make the PLL. Maybe one should better use the crystal without tuning and realize a virtual digital PLL.

So i made a test board with a Nucleo-STM32L432KC module. I replaced its built in clock by a canned 8 MHz oscillator to drive the MCU clock PLL and the timer 1 clock input directly. That means in order to realize 50 Hz one needs a 160 000 long counter. This is possible by extending the 16 bit timer 1 by its update interrupt handler. One could use three times 53 333 yet in order to get a 10 msec ADC cycle as in the Prema 6048 i implemented four phases: 60 000, 20 000, 60 000 and 20 000. Phase adjustment is by cycle count of the last phase

Timer channel 1 is used to capture the reference phase derived from a 15 Vac transformer with a passive clipping/filter circuit. This drives comparator 1 that is internally wired to the channel 1 capture. The capture interrupt routine has the virtual PLL.

In order to check the lock i used timer channel 2 as a 10 000 count PWM output. The scope dump shows a stiff lock at 70 000 counts. Blue trace is mains reference signal. Phase detector noise is about 10 cycles or 1.25 usec. In order to check whether i got the cycle counting right, i made it measure the mains frequency in one second intervals and logged that together with the HP 5335 measurement. There is a nice agreement with standard deviation of 0.0015 Hz = 30 ppm.

Regards, Dieter

[dietert1]

The crystal clock together with the agile time division scheme allows the integrator to cycle in sync with mains. In this scheme the total integration time will be slightly variable as in the original Prema PLL scheme and a multiple of actual mains cycles. In the original PLL scheme the meter only counts/sums up run-down ticks in order to digitize the input. In this alternative scheme there will be a division of the total run-down time measured by the total integration time measured. The FPU of the MCU will do the work of the PLL. This way the circuit has less parts and less jitter.

By todays standards the Prema 6048 is a very simple device. Let's study a little what can be done with a modern MCU. The MCUs built in ADC should serve to determine the integrator zero timing with sub-cycle resolution in order to get 8 decimal digits within one second. The STM32L432 ADC does 12 bit at 5 Msps. STM32H7 MCUs come with 16-bit ADCs, so that may be an alternative using similar firmware. I also ordered LT2386 18-bit 10 Msps ADCs, in order to try the same methods with an FPGA - in case an MCU isn't good enough.

Regards, Dieter

[dietert1]

Meanwhile i found that the STM32 timers don't support timer capture with output of the synchronized PWM signal. One could use an interrupt handler for this. Instead i started to use a XC6SLX9 FPGA module and implemented the DDR interface for the LTC2386 18 bit 10 Msps ADC. With the MCU one can use the built in ADC, up to 16 bit and 5 Msps.

It seems that a Prema 6048 derived meter fits onto a 90x160 mm board to run inside the same IP66 enclosure as the ADR1399 reference i showed here https://www.eevblog.com/forum/metrology/adr1399-reference/msg4559587/#msg4559587. Except the meter will use a TEC oven as it generates 2 W of heat instead of the 700 mV or so from the ADR1399 circuit. Running a meter inside a temperature and humidity controlled enclosure will certainly improve it's accuracy.

Here i have a log of a SHT35 sensor inside the ADR1399 enclosure. The log was started after the last modification inside the oven. Due to the size of the enclosure there are temperature variations of +/- 0.02 °C. The step on 15.8. happened after the unit went to another setup in another room. Humidity log showed exponential decay (action of used desiccant bag inside oven). Then there was a rainy period and recently we had dry weather again. Variation about 1 %RH. The ADR1399 enclosure isn't as hermetic as it could be - with its DSUB-9 connector and three binding posts. The sensor isn't calibrated to this level, but for observing changes it is pretty reliable.

Regards, Dieter

[dietert1]

Meanwhile the meter board is partially populated and i made a power supply with a shielded mains transformer: -33 V, -12 V, -5 V, +3,3 V, +5 V, +12 V, +18 V). The design is such as to run everything with minimum heat. 3.3 V is for the FPGA module that includes switchers for 1.2 V and the 2.5 V needed for the LTC2386 digital section. We'll see whether the switchers are a problem.

The dual LTZ1000 reference works as intended with VRef = 14.1876 V and about 5V heater voltage at ambient temperature. The negative reference (same as Prema 6048) is -1.75 V. The PI temperature controller got configured for 28 °C. The front end with the BS supply works, too. It went stable after adding the 470R + 1nF filter shown in imos recent simulations. When feeding the meter input with low impedance, output rise/fall times are about 50 nsec with little overshoot. With the standard input protection and filter this increases to about 1.2 usec.

Regards, Dieter

[Kleinstein]

I like the idea with measuring the mains frequency and adjusting the ADC period as needed. A little more math for the result should no longer be an issue.

In the prema 6048 the input amplifier is working with essentialyl zero at the input. So no need for classic bootstrapping. The circuit needs the separate floating supply and good isolation there however.

A LTC2386 auxiliary ADC may well be overkill. With oversampling this ADC alone may give good enough performance. There should be no need to go super fast if the ADC runs with the rather slow 100 Hz cycle. So there is usually plenty of time for getting the slope(s). The actual feedback part may still use a simple comparator. A high timing resolution for the "zero" (or slightly different ref. level) is only needed for the start / stop part. This part can also get away with some latency e.g. to read the ADC and process the data. Chances are one could set the start stop level to before the feedback switching and this way get 2 readings, one just before and a second after the ref. switching.

[dietert1]

First change from the Prema 6048: I moved polarity switches to the input.
Second change: Bootstrapping the input stage avoids the two separate isolated supplies of the Prema frontend. Like the Prema the ranges are by switching the resistor that converts input voltage to integrator current.
Except for the lowest range there i added a NOMC 10:1 divider to get 10x gain - as proposed by ECHO88. There is a dual mosfet relay AQW210 to turn bootstrapping on/off.
As the reference is positive, the input section works between -33 V and +12 V supplies. Probably the circuit can be made with -50 V as well. imos recent simulations resemble the circuit, except i put some zeners to absorb excessive input. Though i forgot an overvoltage sensor to disconnect the input relay in case of overvoltage.
The board also has the filter and a comparator for synchronizing ADC operations with mains. That part of the FPGA is ready.
At full range input the integrator sweeps between 0 V an 12 V. There is a comparator in addition to the fast ADC. The board also has a 10x slope amplifier that may be completely unnecessary considering the resolution of the ADC. With that gain the ADC common mode voltage of 2 V becomes 0.2 V. The comparator also switches at 0.2 V, so there should be good ADC data near the zero. One can study that in the digital domain, maybe using some denoising filter. There are provisions for a UART interface with isolation.
Yesterday i started to build the hermetic TEC oven. The cabling is pretty wide as it includes the FPGA JTAG, many test signals and some spare wires. Threefold overhead.

Regards, Dieter

[dietert1]

After wiring a lab power supply to the frontend and a 3478A meter to measure the deviation of the OPA189 buffer output from input i got the appended diagram. During the test the 10 KOhm resistor for the integrator current was selected as a load of the OPA189 output (12 V range).
The -0,105 uV/V slope of the line fit gives a 141 +/- 4 dB gain estimate while the open loop gain spec of the OPA189 is 170 dB (for +/- 18 V operation). The test has about 30x gain missing. The diagram should become near flat (constant offset).
Offset voltage is 2.9 uV, with a +/- 0.8 uV typical datasheet spec. My test setup isn't all low thermal EMF.
At -12 V to -24 V input voltage up to 10 uV additional deviation appears delayed as if something needs time to heat and then the heat causes that deviation. Need to work on that, like heat testing each component. Another thing i want to try is using 2x TL431 instead of zeners to make low TC bootstrap supplies. Another one is adding a pnp emitter follower to reduce the OPA189 output load. The Prema 6048 had a second opamp in its frontend.

Regards, Dieter

[iMo]

..Another thing i want to try is using 2x TL431 instead of zeners to make low TC bootstrap supplies. ..

Perhaps an 1N4148 is series with each zener would help..
PS: also not sure how the 431 will behave there (stability).

[Kleinstein]

A thermal effect on the OPA189 due to loading could be an issue. A 10 K load with a 12 V output range is quite some load, even with an only moderate supply voltage.
Loacal heat on chip can be different than just a global temperature change.

When using a bootstrapped supply I am not even sure that just the regular DC gain applies. The BS part may add to the gain. With a RR output stage it may be anyway a kind of transconductance that is limiting more than voltage gain.

An extra current buffer is definitely a good idea, as a BS supply often does not work that well with a strong load anyway. Depending on how the BS supply a made this part can be additional load (at least in the simple form the iMo showed).

I am not so sure the OPA189 is such a good choice for the input. It is low noise, but also relatively high bias current. I would conder the OPA387 with still low noise, but less bias and current noise and also lower supply current.

[dietert1]

After replacing the zener by TL431 the frontend BS schematic will look like shown. Different from imos drafts my design had constant current sources. As +Vcc is 12 V in my case, the LED gets about 1 mA with Uf = 1.9 V. The difference zener current between positive and negative BS was measured to be 26 uA. That would be the DC load of the OPA189.

Regards, Dieter

Edit: Probably C38 needs to move somewhere else to guarantee phase margin for the regulator.

[dietert1]

After adding a pnp emitter follower with a 10 KOhm pullup to the positive bootstrap supply the OPA189 works as expected. There are no more signs of residual slope. With the current setup the detection limit is about 0.3 uV in 24 V (10E-8).
Offset and delayed deviation vanished after i changed the probing location 1 cm away from the 10 KOhm integrator resistor that heats most. Seems like its self heating generated thermal EMF. It remains for later to see at which level this affects the voltmeter. The integrator resistors might need heatsinks.

Regards, Dieter

[Kleinstein]

Thermal effects at the resistors can be an issue, especially with a relatively high current (e.g. up to 2 mA with 20 V and 10 K). A heat sink and even temperature regulation alone may not be enough to counter power coefficients. Heat compensation may work with some resistors (e.g. a thin film array like TDP) but may fail with others, especially BMF types with more thermal resistance between layers.

Thermal EMF at resistors can be an issue - it depends on the resistor types. Symmetry in the thermal layout can help, but may not allways be practical.

[dietert1]

Currently the precision resistors are Vishay S102K (2 ppm/K). The four blue 68K1 resistors in the reference are SFERNICE RCK02 (5 ppm/K) and the big 750K for the negative reference is labeled S105D. For most resistors there is enough space to replace them by better hermetic foil resistors or to apply some heatsink if necessary.

Regards, Dieter

[miro123]

First i made a log of our 50 Hz mains frequency using a HP5335 meter. Gate aperture of the HP5335 is 0.5 sec. A crystal cannot be tuned enough in order to make the PLL. Maybe one should better use the crystal without tuning and realize a virtual digital PLL.

Sorry for my late reaction. I've saw this thread.
You cannot assume that
1. Grid frequency is slow moving variable
2. Grid phase is continues variable
Most country standards for grid connected devices cover it - German VDE is good starting point.
- why phase is not continues variable? - What happen If you switch on big load - E.g huge electric motor?  UK grid code G59 requires handling of +-60deg phase jump
- The grid frequency is heavily modulated nowadays - Partly doe to renewable energy sources. They implement active active /LOM-lost of mains/ Anti Icelanding. The core is inducing reactive power with certain pattern - shake the grid left or right - in case of LOM frequency goes much higher that grid-tied.
- Even in old days the grid frequency was not constant it relies on  averaging the speed of many mechanical turbines.  I'm not mentioning the non linear behavoiour of electric machines used on power plants.

PS: Many STM32 devices offer HR timer e.g. stm32 G4,H7 or F3

[dietert1]

For a high resolution meter one wants to run the conversion process in sync with mains in order to suppress hum as far as possible. Nothing new. The Prema 6048 does it with an analog PLL, using a RC VCO with its extra phase noise. In order to use a fixed frequency crystal oscillator one can use a digital scheme that measures PWM on and off times both in units of crystal periods and determines the ADC result by floating point division. At the time they avoided that in the Prema with its 8 bit MCU.

I cannot confirm claims of mains phase jumps of 60°. Instead i observed phase noise in the 10 or 20 usec (fractions of a degree). My frequency log above measures the frequency variations to be small, though one can see the 15 minutes pattern that results from electrical power trade.

Hum suppression suffers from another problem: Often hum is phase shifted as it is from capacitive or inductive pickup. A good meter should have some kind of hum evaluation and an adjustable phase offset for the mains PLL.

How to output the synchronized timing of a STM32 timer capture? I mean for an ADC one needs a PWM determined by the timer capture of some comparator. I could supplement the MCU with a sync circuit (flip-flop and some gates, maybe CPLD) to make things work. Instead the MCU went for a FPGA - in order to implement the LTC2386 DDR interface.

Regards, Dieter

[Kleinstein]

To control the PWM signal via the extra comparator one can use the timer triggerfunction, though this adds a little (on the order of 10 cycles) delay. I use this is my ADC implementation. The comparator is used to trigger and reset the timer that than generates the PWM signal. Another channel of that some timer can generate a trigger signal to be measured by the capture fuction of another timer. So the sequence is more comparator -> capture -> PWM , but as comparator ->  restart timer -> PWM -> capture.
It can depend on the µC type, AFIAK not all support using the comparator as a trigger source. So with some models one may need an external comparator or route the comparator signal externally back to a trigger input pin.

With a µC and maybe also for the FPGA one may want an external flip flop for synchornization. There can be clock delays internal to the µC that depend on the internal state or IO pins. This can add jitter and also nonlinear effect. With the rather slow (e.g. 100 Hz) PWM as used in the prema meter this may not be as bad - with the much faster (e.g. 100 kHz range) PWM with the simple 2 case modulation this was noticable.

For the mains hum suppression there is no real need to have a specific phase for the start / stop. Having a difficult spot near mains synchonous interference (e.g. a SCR triggering in a near by circuit) may add noise though, but it is hard to predict where those difficult spots are. With the digital phase sync mode one has the freedom to add phase shift. With the 100 Hz PWM clock as in the 6048 one would anyway have 2 phase values to use and may compare the noise for both.  With rather long integration (a few seconds) hum suppression should be quite good anyway, especially if the period is adjusted. So I would not worry that much about mains hum - really critical measurements tend to be shielded. The BS supply for the input amplifier would eliminate the isolated transformer winding as a source of hum.

[dietert1]

Yes, accepting latency one can use some tricks with the STM32. One could also use a comparator interrupt to terminate the run-down via the PWM register. For the time being it's the FPGA module with the LTC2386 ADC. No need to optimize now.
Today i mounted a TEC2-19006 to the bottom of the aluminum enclosure. It got 1 A of reverse current at about 5.6 W to heat the glue and get it liquid and thin. The FLIR image showed a temperature difference of 24.5 K. Without thermal insulation and at about 22 °C ambient temperature the open aluminum enclosure exhibits about 3 K temperature difference between its hot and cold spot.

The heat output of the meter board is 2 W max and i assume the TEC will eventually run at about 6 W of electrical input, except then the cold side will be at the enclosure. The shielded mains transformer is good for 12 VA. Hope it will work.

Regards, Dieter

[Kleinstein]

2 W is not a lot of power, especially not with 2 x LTZ1000 reference and a possibly somewhat power hungy FPGA - maybe the FPGA is outside the regulated area.

A lower temperature helps with semiconductor leakage currents at the front end. A temperature a little high then the environment would on the other side help with humidity as the RH goes down. High humidty can increase the surface leakage on plastics. It may be a good idea to aim for less than 50-60% RH, which is easy with a temperature of some 10 K above ambient.

24 K temperature difference across the TEC looks like rather large - maybe go for a larger heat sink / fan on the ambient side. 

[dietert1]

TEC2-19006 is a 40x40 mm double TEC with more temperature difference.

The FPGA is a Spartan6 we had and it needs to be inside the oven in order to read the high speed ADC via a 100 MHz DDR interface with two lanes. Until now the FPGA consumes about 700 mW. This may still increase a little. Don't know yet whether its JTAG will work from the outside as the cable length will be like 30 or 40 cm.

The double reference runs from a supply of 18 V with half of that available for each of the two heaters. The negative heater terminal of the upper LTZ is at 9 V - about 1.9 V above its substrate. Last time the heater voltages were 5 V and 5.6 V. At 250 Ohm heater resistance that gives a total of 225 mW. Later the LTZ1000 references can be configured to run like 10 °C above oven temperature.

The ADC consumes about 110 mW. So the 2 W max should be safe.

Regards, Dieter

[dietert1]

Meanwhile i made a TEC output stage for the oven controller, see schematic. For efficiency the circuit uses a Polulu SIC473 switcher. Its voltage control by (around Q5) maintains a headroom of about 1 V above the required TEC output voltage.
The circuit has the usual mosfet bridge for the two TEC polarities, so it will heat and cool. There are two opamps as current regulators. D1 and R11 let IC1B decide the polarity. Due to the delay of the opamps when coming out of negative output saturation the circuit handles polarity change without bridge   shoot-thru. The screen dumps show the two opamp outputs with a +/- 12 V sweep as input. The dead time is about 1 msec.
With additional cooling the ciruit can be used for higher currents. The switcher spec is 5 A.

Regards, Dieter

[dietert1]

The oven and its thermal housing are ready. I used a 40 x 10 mm copper bar for heat transfer from the bottom of the TEC to the heatsink. The power supply and the TEC driver were assembled into a separate unit. There is enough space for a little MCU board and the isolated RS-232.
Yesterday i wired a first oven test with a dummy load (330R resistor with heatsink) inside the oven. After tuning temperature controller dynamics i saw that for 28 °C nominal oven temperature and 22.5 V => 1.53 W dummy power the TEC finally ended up heating with 0.55 V or about 0.12 W electric input. All this at about 17.5 °C ambient air temperature. Due to the low thermal resistance of the TEC and its heatsink the oven doesn't even reach 28 °C with the dummy power and needs additional heating by the TEC! When i turned off the dummy power, the TEC voltage went up to 1.27 V or about 0.62 W input. The TEC controller with its current configuration can deliver 3.6 W for heating and for cooling, so the oven seems to work better than expected.

Regards, Dieter

[iMo]

What is the tuning capacitor near the transformer good for?

[dietert1]

The transformer has a shield between primary and secondaries. If we connect the shield to guard, then the secondary will inject hum current between the DC supplies and guard. The trim cap supports compensation down to levels of about 20 nA. It works for a certain orientation of the mains plug.
This is with 220 V 50 Hz L and N mains. I tried to find a scheme that allows reversal of the mains plug without readjustment but gave up on that.

Regards, Dieter

[dietert1]

To study the oven behaviour i noted down some measurements at different ambient temperatures and at different power levels of the dummy heat source inside the oven. Then i fitted a model that has a linear term for the TEC (Peltier effect), a quadratic term (TEC self heating) and the dummy power. The model has three parameters and the fit determines them minimizing the standard deviation of the oven temperature.
Oven temperature estimated by the fit is 28.4 °C where 28 °C was the configured value. The model allows an estimate of the ovens operational limits. Within 0.5 to 2 W power consumption of the meter board the allowed ambient temperature range should be about 0 to 40 °C.
This is a "quick and dirty" method and easy to improve, e.g. by measuring the TEC current instead of voltage and by observing the heatsink temperature as well. Or one could test the setup inside a chamber that directly sweeps the 0 .. 40 °C ambient temperature range.

Regards, Dieter

[dietert1]

Meanwhile the second board is partially working and today i started looking at the integrator. As a test i wired the -1.76 V of the negative reference to the 2 KOhm integrator resistor of the 2.4 V input range.
The scope dump shows the 50 Hz mains comparator in C4. C2 is the integrator output and C3 the comparator that stops rundown when going low. One can see a pretty chaotic behaviour caused by the simple PWM control method: Start rundown at middle of 10 msec interval + 1 msec, stop on comparator low or 1 msec before middle of next 10 msec interval. The maximum rundown duration is 8 msec. The integrator exhibits a nice sweep up to about 17 V.
The Prema 6048 uses this simple minded PWM method and it's the reason why there is only 20 V of its native 70 V ADC range available. Hope to improve that for my design.

Regards, Dieter