It occurred to me that with this setup I could easily measure the leakage across the Panasonic open relay contacts (and veroboard) which will inform the next project.
I had to shield the input cable to reduce the stray capacitance, and I put a simple copper-tape-covered-cardboard screen over the top of the jig so that I didn’t have to hide under the bench, and stay still, as I have on earlier tests using a 1 nF integrator capacitor.
I upped the sample rate on the scope, giving 300,000 data points, then decimated it down to 6000 points using an MFC Visual C++ program.
The capacitance meter was tested against my 1.000nF ±1% reference polystyrene capacitor. The reading was 1.001 nF. Hence the 1 nF integrator capacitor, measured at 0.928 nF, is reasonably expected to be within ±1% of the measured value.

The droop on the integrator alone was 45 µV/s with say ±2% for the buffer, and another ±2% for the scope.
The
nominal bias current is then 928E-12 x 45E-6 = 42E-15. Let’s call it
42 fA ±10%.
For +20 V leakage we have 340 µV/s + 45 µV/s = 385 µV/s
For -20 V leakage we have -418 µV/s + 45 µV/s = 373 µV/s
The average is 379 µV/s, which equates to a current of 928E-12 x 379E-6 =
352 fAThe
leakage resistance across the board and relay body is then 20 / 352E-15 = 57E12 =
57 T ohms ±10%
[EDIT: Addition]If you think about it some more, you will realise that this ‘live leakage current’ is also critical to the evaluation of the jig. Since the 50 V is usually left connected to the open relay contact, this leakage current is 21x greater than the opamp leakage. Clearly we could use a second relay contact, and an intermediate pull-down resistor, or simply turn the power supply down during most of the test, but it does mean we have possible leakage paths around 30 T ohms effectively across the capacitor under test. In this case that is a tolerable amount of leakage, but we needed to have tested it to prove the point.