PWM new article from S. Woodward

[RandallMcRee]

Just saw this in EDN 

Thought folks here would be interested.

https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction-revisited/

[guenthert]

Thanks for the pointer, but if I understand the comments correctly, one would want a Sallen-Key filter anyhow for better ripple suppression and faster settling times (at the cost of marginally higher complexity and an OpAmp [1]).  Is that right?



[1] https://www.edn.com/design-second-and-third-order-sallen-key-filters-with-one-op-amp/

[Kleinstein]

I had looked at the current more compensation circuit in a simulation and AFAIR the compensation part had the same effect as an addition 1st order filter stage. Same attenuation and same extra settling time. As digital inverters are relative cheap it could still be wort it, but the response of 1 st order filters is still not ideal and a proper 2nd order filter may be better performing.
The simple 2nd order Sallen-key filter can have the problem of direct feed through via the capacitor in the feedback, if the OP amps is not very fast. So ideally one would have a 3rd order filter with an extra passive stage in front.

I don't think the voltage compensation would be significant different. As a first crude guess mainly a shift in the cross over freqency and this way faster settling but likely more ripple to start with.

[dietert1]

Isn't the proposed compensation circuit equivalent to a second order filter? Without compensation it's a 1st order filter, with compensation we have the equivalent of another 1st order filter. With two resistors and two capacitors it should be second order.

Regards, Dieter

[spostma]

thank you for the link!
Stephen Woodward is the most creative analog designer I know.
Check out all his design ideas on EDN!

[Ian.M]

Its a bit early for April Fools articles!
If you tweak the time constants for equal ripple to the simple cascaded two stage passive RC alternative, it doesn't settle significantly faster, nor does it settle faster than his 2017 offering.  I've attached a LTspice SIM comparing the various proposed circuits.

TLDR: It doesn't appear to be worth it even if your MCU gives you complimentary PWM outputs 'for free'! 

[PCB.Wiz]

Its a bit early for April Fools articles!
If you tweak the time constants for equal ripple to the simple cascaded two stage passive RC alternative, it doesn't settle significantly faster, nor does it settle faster than his 2017 offering.  I've attached a LTspice SIM comparing the various proposed circuits.

TLDR: It doesn't appear to be worth it even if your MCU gives you complimentary PWM outputs 'for free'! 

I'll bump this with another tweak.
The classic 2 stage passive LPF uses a lazy equal R equal C choice, but that actually means the second stage loads the first and compromises the roll off.
If you do not mind choosing a lower loading second stage, you can get an improvement with no added parts.

Attached spice shows a 2nd stage loading of 2x improves ~ 10% and a loading of 4.5x (and tuned for equal ripple) gives a ~20%  35~43% gain in speed over an equal-value RC pair, now much faster than the EDN offering, yet with fewer parts. 
A fully buffered second stage example using an opamp shows ~ 55% improvement over equal-value RC for these ripple settings (+/- 1/256th of full scale).
A design may have the spare opamp for free.

Addit : Updated circuit to include OpAmp buffer reference point, to show loading effect.