Remote controlled DMM DCV INL tester based on voltage divider idea

[Kleinstein]

I analyzed a few more of the data, as an example on how such a curve may look like. The voltages are set by sets of alkaline batteries (some older and thus not all 1.5 V).
The curve shows the residual of the sum test for a few test points in the 20 V range (the prime range of the meter). The actual ADC sees +U/2 and -U/2 and thus kind of does an internal turn over.  So the turn over error is very small and the 2 points measures with a negative voltage are also just symmetric.  So the error curve should mainly have the odd powers.

The fit  with 3 odd powers  is a bit of a stretch with the limited number of points. Only linear and 3rd power however does not give a good fit.
The blue curve would be the err polynominal converted to INL error (with the linear slope adjusted to about overall low error). Due to the limited number or points this is more for demonstration, not a serious result.

The data so far are a bit crude, but with an easier way to change the voltage and thus more points with less user interaction the test method looks promissing.
Even the batteries as test voltage look OK, though not great and much of the drift can be corrected. The demand main on the reference for this test is low noise. Low drift is not really needed, though it could help a little. Other tests, like the originally planed sum of many similar steps would be more sensitive to drift (at least more difficult to correct). So low drift can still be desirable.

[guenthert]

If I'm not mistaken, one difficulty lies in distinguishing actual non-linearities from offsets due to thermal EMF.  I'd think the method using a resistor string has the advantage there as it allows to reverse polarity of the driving voltage w/o detaching/re-attaching a probe.

[Kleinstein]

If done with moving around cables the thermal EMF would indeed be a big problem. The test should use something like relays or CMOS switches to switch between the 3 or 4 voltages to measure. This are 2 single pole, double through switches: one each for the high side and low side for the DMM / DUT.  The nice point with the test (4 voltages including the zero) is that in the sum each of the switch contacts enters twice with a positive and twice with a negative sign. So any fixed offset or thermal EMF at any of the swich connectors will cancel out.  For the automated test the thermal EMF is thus no longer an issue.

A polarity reversal could than be done manual (change the connections) for a separate run. So it could be enough if the test source is one polarity. It does not matter if the offsets / thermal EMF would change between the runs. Also a slow drift during repeated test sets are not am issue. A nice point with the sum test is that only 4 readings are critical as a set and long term drift is not that critical.


One weak point with the test is reference noise, that can make the test a bit noisy and thus slow. At least the LM399 in my case is a real issue and due to the jumps they produce quite some outliers and thus makes the test slow. So one shoud have a really low noise reference (e.g. LTZ, ADR1399 ?, LTC6655) at both the external source and DMM. With only 4 voltage readings for a sum one can at least limit the effect of very low frequency noise - the test with the resistor string would be even more sensitive to ref. noise due to a longer time for a set of readings.

Another weak point is the assumption of a smooth INL curve. So a more local / jagged INL contribution (hard INL) can interfere with the calculation back the the INL curve. One can still get the residual error from the sums as spot tests for the linearity, but it would be hard to really calculate back to the INL curve. It would at least need quite some test voltages to hopefully average out more local effects. For the more loacl INL errors one would need a separate test.

The sum of equal steps from the resistor string definitely has an advantage that the interpretation of the result is easier. One kind of gets a limited set of points for the INL curve. One however still has the assumption that the INL error for the step size measurements (e.g. 5-10% of FS) is about equal. The number of points in the curve is limited as with very small and thus more  steps more errors add up and noise / drift gets more of an issue. Because of the drift one would likely want automated switching of the connections and thus quite some relays / CMOS switches.
The problem with the hard INL is similar, just only for a more limited range around the step size. With the limited number of points / steps in the string the averaging it out is bit more tricky.
Ideally one would do both tests - they test different aspects of the INL and at the very low levels and extra check is a good thing.

[iMo]

What if I would have got, for example, two 0..12V output 12bit DACs, both fed by the same Vref, and the DUT/meter will be wired between the DAC's outputs floating. Will that help somehow?

[Kleinstein]

The 2 DACs would allow getting positive and negative voltages. One could also average out errors of the DAC be using different combinations for nominally the same result, at least with many values in the middle. Still the avearge of 2 12 bit DACs would not be that good to be really helpfull as a highly linear source.

There is a way to use the 2 DAC also as a stack of voltages, but as far as I see with an extra complication of 2 types of step (e.g. a positive and negative). At least I don't see a good way to use it to replace the string type test.


For just the simple sum of 2 equal voltages test it would only need 1 DAC. 12 Bit could be good enough, if the DAC is low noise (e.g. many current output types). Depending on the meter to test one may want additional scaling (e.g. for a 20 / 10 / 2 / 1 V range), than a divider with just 2 about equal resistors (nothing special needed just cheap thin film to avoid extra noise). I would prefer a buffer amplifier for the divider center, especially if the DMM to test is not super low bias. The buffer should not be tricky for high voltages like a 10 V or 1 V range , maybe with 100 mV and less.
The main part for the test are the 2 switches for the DMM inputs - if not at the DMM this could be DMOS switches like DG419 / DG413 with the reference. I would consider a DIP version in a socket and than skip on extra protection.
For the links from the voltages  to the switches one may want some jumper options to allow also the turn over version.

[CurtisSeizert]

Another question is what does error function phisicaly represent - error at 5V, at 2.5V or combined?
My point is that It requires calculation the total uncertainty of proposed solution. I see a plenty of error sources - without calculation is hard to say what for accuracy are you gonna achieve.

I haven't tried to analytically determine the uncertainties in this, but I did write some code in python to see how it does when there is noise. I don't consider Ib dependence on Vin to be something that is necessary to confront here since that can be measured separately. The equations I presented are to determine the transfer coefficients at V(DAC,GND). The code is kind of a mess, but here it is:

Code: [Select]


import numpy as np
import numpy.polynomial.polynomial as nppoly
import matplotlib.pyplot as plt

def displayplot(title=None):
    plt.figure(dpi=600)
    plt.plot(Vin, uV_errors, label='Noiseless')
    plt.plot(Vin, uV_errors_n, label='With noise')
    plt.plot(Vin, uV_errorscalc, label='Calculated')
    plt.plot(Vin, uV_errorscorr, label='Corrected')
    plt.legend()
    plt.xlabel('Voltage')
    plt.ylabel('Error (uV)')
    plt.grid(visible=True, which="both", axis="both")
    plt.title(title)
    plt.show()

rng = np.random.default_rng()

#parameters
numpts = 101
Vmax = 10
Vmin = -10
divratio = 0.5
sumfitorder = 5
revfitorder = 4

'''transfer function coefficient array as
deviations from linearity in ppm
y = A + Bx + Cx^2 + Dx^3 + Ex^4 + Fx^5
B represents gain error and cannot be calculated.
The index of the array is the order of the term.'''

tcoeff = [-0.6, 0, 0.0035, -0.0013, 0.0000097, 0.000006]
calcdcoef = np.zeros(6)
torder = 5
stdev0 = 0.03 #zero order noise, uV
stdev1 = 0.05 #first order noise, uV


#calculated parameters
Vint = (Vmax - Vmin)/(numpts - 1)

Vin = []


'''Calculate input voltages'''
for x in range(0,numpts):
    Vin.append(Vmin + x * Vint)
   

'''Calculate low divider voltages'''
Vin_divl = []

#calculate input voltages
for x in range(0,numpts):
    Vin_divl.append((Vmin + x * Vint)*divratio)
   

'''Calculate high divider voltages'''

Vin_divh = []

#calculate input voltages
for x in range(0,numpts):
    Vin_divh.append((Vmin + x * Vint)*(1 - divratio))
       

   
'''Calculate error voltages'''

uV_errors = np.zeros(numpts)


for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errors[i] = uV_errors[i] + tcoeff[x] * Vin[i]**x - calcdcoef[x] * Vin_divl[i]**x
       
'''Add noise'''

uV_errors_n = np.zeros(numpts)
uV_errors_nr = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_n[i] = uV_errors[i] + stdev0 * rng.standard_normal() + Vin[i] * stdev1 * rng.standard_normal()

for i in range(0, numpts):
    uV_errors_nr[i] = uV_errors[numpts-i-1] + stdev0 * rng.standard_normal() + Vin[numpts-i-1] * stdev1 * rng.standard_normal()
       
       


'''Calculate reversal error voltages'''
uV_errors_rev = np.zeros(numpts)
for i in range(0, numpts):
    uV_errors_rev[i] = (uV_errors_n[i] + uV_errors_nr[i])/2
   
#offsetrev = np.average(uV_errors_rev)
#uV_errors_rev = uV_errors_rev - offsetrev


revfitorders = [0,1,2,4]


revpoly = nppoly.polyfit(Vin, uV_errors_rev, revfitorders)
fit_coeffs = nppoly.polyfit(Vin, uV_errors, sumfitorder)



calcdcoef[0] = revpoly[0]
calcdcoef[1] = 0
calcdcoef[2] = revpoly[2]
calcdcoef[4] = revpoly[4]


   

'''Calculate low divider error voltages'''

uV_errors_divl = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_divl[i] = uV_errors_divl[i] + stdev0 * rng.standard_normal() + Vin_divl[i] * stdev1 * rng.standard_normal()
    for x in range(0,torder + 1):
        uV_errors_divl[i] = uV_errors_divl[i] + tcoeff[x] * Vin_divl[i]**x - calcdcoef[x] * Vin_divl[i]**x
       
       
'''Calculate high divider error voltages'''

uV_errors_divh = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_divl[i] = uV_errors_divh[i] + stdev0 * rng.standard_normal() + Vin_divh[i] * stdev1 * rng.standard_normal()
    for x in range(0,torder + 1):
        uV_errors_divh[i] = uV_errors_divh[i] + tcoeff[x] * Vin_divh[i]**x - calcdcoef[x] * Vin_divl[i]**x
       

'''Correct total voltages'''
for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errors_n[i] = uV_errors_n[i] - calcdcoef[x] * Vin_divl[i]**x

'''Calculate sum error voltages'''
uV_errors_sum = uV_errors_n - uV_errors_divl - uV_errors_divh
offsetsum = np.average(uV_errors_sum)
uV_errors_sum = uV_errors_sum - offsetsum


sumfitorders = [0,1,2,3,4,5]
sumpoly = nppoly.polyfit(Vin, uV_errors_sum, sumfitorders)
tsumcoef = np.zeros(sumfitorder+1)
tsumcoef[2] = sumpoly[2]/(2*divratio - 2*(divratio**2))
tsumcoef[3] = sumpoly[3]/(3*divratio - 3*(divratio**2) + divratio**3)
tsumcoef[5] = sumpoly[5]/(5*divratio - 10*divratio**2 + 10*divratio**3 - 5*divratio**4)

calcdcoef[3] = tsumcoef[3]
calcdcoef[5] = tsumcoef[5]

'''calculated transfer errors'''

uV_errorscalc = np.zeros(numpts)

for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errorscalc[i] = uV_errorscalc[i] + calcdcoef[x] * Vin[i]**x
       
uV_errorscorr = uV_errors - uV_errorscalc


displayplot()
print("Coefficients: ", tcoeff)
print("Calculated coefficients: ", calcdcoef)

The code uses reversal to determine the offset and second order coefficient then uses that to apply a correction factor for those terms before doing the regression for the sum error. This seems to work a bit better than doing everything separately as there are fewer degrees of freedom for reversal, which only has even order coefficients. As expected, the more points you get, the better the immunity to noise. I have attached a couple plots from running the script with some random coefficients I had chosen, one where it does well, and one where it does poorly. Noise is modeled as conversion noise that is constant at all input voltages and reference noise that scales with the input voltage.

I have nearly finished up the board I am currently working on, so I will design something along these lines in the coming weeks.

[Kleinstein]

The polynominal fit can get a bit tricky and increasingly sensitive to noise, when higher orders, like 7th or 9 th order are inlcuded.  If the actual INL is not well described with a low order polynominal one might have to include those higher terms, at least from the theoretical side. Ignoring them would not improve the result, but make it worse.
So if the INL is not well descibed by low order polynominal the calculation back may become tricky. The factors to go from the cn to an coefficients for a 1:1 divider should be - 1 - 1/(2^(n-1)-1) for n > 1 and thus convert to 1 relatively fast. With possibly opposing signs and relatively large values this could still be an issue for the higher powers.

Test with the sum from the half way point still makes sense to check, it may just be hard to calculate back to an INL curve if the curve is not well behaved.


For the hardware side I did a few more tests. One point that may be interesting is that the impedance of the divider can make a difference. This is especially if the DUT or possibly the switching part is not super low bias / leakage. In my case a series resistor of 6.8 K for the center voltage changes the sum of the 4 readings by some 1.5 µV.  An extra buffer for the divider voltage would essentially eliminate the effect. Without a buffer a test with an extra series resistor may be a good idea to check for the approximate effect of output impedance.

[miro123]

I am still struggling with HW implementation. I did simple mistake.
I have MAX5216 available, but I overlooked the datasheet noise section.
DAC output is really very noisy and useless.  Reducing the BW does not help a lot.
Actually the datsheet has already described. It is my fault.
Vn= 73nV/sqrt(Hz) @ 1KHz
Vn= 70nV/sqrt(Hz) @ 10KHz
Vn(0,1..10Hz) 3,5uVpp

I have looked for low noise DAC but their price is quite high for such simple hobby project.
Doe somebody knows - low noise DAC, available on stock and with reasonable price?  Or do I  ask a lot? :-)

[Kleinstein]

I have also looked at low noise DACs. A good choice are the current output DACs and there are many similar types to choose from. An example is AD5443 (12 bit) and AD5446 (14 bit).
The noise should mainly be set by the resistance and OP-amp for the output (e.g. OPA207) - the slight unknown is if the resistor part has significant excess noise. The example noise performance in the DS uses a rather fast OP-amp with lots of 1/f noise and the LF part is thus dominated by the OP-amp.

[julian1]

I tried in the past with dac8734 (1uV RMS 0.1-10Hz) but it was a bit noisy.

For AD5444/5446 -
ref input can be +-10V. which means using a ~7V ref is OK.
the multiplying r2r dac outputs are limited, to VDD, max +7V.
But R2 working as an extra resistor in front of the internal Rfb,  can add gain for both the unipolar and bipolar reference circuits,
So this would work for eg. +-10V output.

What would be a good configuration for sum tests?
One could have one multiplying dac with bipolar output to create the first voltage.
And also use the output as input ref for a second multiplying dac to create a controllable buffered divider.

Alternatively, just one multiplying in a bipolar configuration - followed by a fixed divider (eg. 10k,10k) to create a second midpoint voltage would be enough.

[Kleinstein]

The basic configuration for the multiplying DACs is with some 10 or 7 V reference and than 0 to -10 or 0 to -7 V out. So an output gain of  0 to -1.
The supply to the chip is for the switches and the ref. voltage can be higher and even negative. It is a bit tricky to directly add gain, as Rfb is matched to the resistors in the R2R DAC part. So gain would be relatively separate from the DAC. The bipolar version is a bit tricky with extra precision resistors needed.
One may not even need a negative sign. For the negative half one could just change the wiring from the meter to the tester. This would mean running the test as 2 parts.
An extra inverter for an alternative signal with the other side also makes some sense (see below).

A main case for the sum test is having 1 voltage and half the voltage. It would be relatively few divider ratios that really make much sense. So I see little sense in a 2nd DAC for this.
A 2nd DAC may be usefull for other tests, maybe getting close to the chain of voltages as in the original idea: One DAC sets the even voltages and the other the odd ones. For the overall test one would also have ground as a 3rd path for the switches to the DUT terminals.
With buffered signals, leakage would be not critical als relatively simple CMOS switches (e.g. DG411) would likely be good enough for switching.
The general setup could be 2 MUX chips like DG408/9 and a bunch of test signals to choose for both sides. The question may be if one wants protection (one side can be enough) towards the DUT(meter) or take the risk of possibly damaging the switches(e.g. from ESD or a short).

If the 10 V range is enough one could use just the DAC output and a divider. It could make sense to have a buffer for the resistive divider to avoid a loading effect. I would consider a small offset the lesser problem than the output impedance of the divider.

For a larger (e.g. 20 V) range one could consider driving both sides and use an extra inverter after the DAC to kind of replace a 1:1 divider by some effective gain of 2 for the signal between the positive and negative output and ground as the center point. Compared to normal gain this would not need a higher supply and may be more convenient with CMOS switches to have the same GND as the DAC.
This way one would also have the other sign available for other tests.

So possible test signals to the mux chips could be:
1) the DAC output  (e.g. 0 ... -10 V)
2) inverted DAC out   0 ... 10 V
3) GND
4) 1:1 divider from DAC    + buffer  (e.g. 0... -5 V)
5) optional:  1:1 divider from - DAC  + buffer  (e.g. 0... 5 V)
6) possibly a 2nd DAC
7) possibly the raw 7 V or 10 V ref.
?

[julian1]

Is there any way to guess at the possibility of excess resistor noise - for different part choices?

Rfb is a proxy for the values of all other switchable resistors.
The size of Rfb varies, but lower values (5k versus 7-12k) may risk more thermal effects.

Judging by max VDD they all use typical cmos process nodes
It appears there are many ways to do resistors,
https://aicdesign.org/wp-content/uploads/2018/08/lecture07-140310.pdf

But I think only metal thin-film has good enough TC, to meet part datasheet specs, so perhaps thin-film could be assumed?
Maybe tests are the only way to know for sure.

As Kleinstein notes, the datasheet 1kHz noise figures are likely meaningless for LF DC, but relate more to the fast op-amps used for test setup circuits.

The AD part, is nice in that it brings out a separate gnd for the resistors.

AD5444_5446
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
Fig. 39 shows output noise ramping at lot <1kHz / AD8038.
Rfb 7-11k.
DS states resistors are thin film - "consideration the effect of the temperature coefficients of the thin film resistors".

RM10 mssop 10.   0.5mm pitch.

LTC1595
Equivalent DAC Thermal Noise Voltage Density (Note 10) f = 1kHz 11 nV/√Hz
Rfb 5-10k,  7k typ.
soic-8.   1.27mm   4mm width.

DAC8811.
Output spot noise voltage f = 1 kHz, BW = 1 Hz 12 nV/√Hz
doesn't say Rfb, but probably the same as dual DAC8812, which gives Rfb= 5k.
dgk = vssop.  0.65mm.

DAC7821  12bit dual
Rfb  8 to 12k.
tssop-20.

[julian1]

Sorry for the edits.   

Got a nice statement here from AD, that white/thermal noise is dominant,

"Low noise — the AD54xx and AD55xx family of IOUT DACs utilize low impedance architectures. These are inherently low noise architectures dominated by the thermal noise of the RDAC resistor."

https://www.analog.com/media/en/news-marketing-collateral/solutions-bulletins-brochures/AnalogMultiplyingDACs.pdf

And the resistors are silicon/chromium thin-film,

"The AD5449 (and the AD5415) are dual CMOS multiplying DACs (MDACs). They are
made with silicon/chromium thin film resistors and CMOS switches. Since the
resistance of the CMOS switches is much lower than that of the resistors in the
network the noise of such devices is quite close to the thermal noise of the
resistance. "

https://ez.analog.com/data_converters/precision_dacs/w/documents/3490/ad5449-output-noise-spectral-density

[Kleinstein]

The white noise part from the normal resistor noise should not be that important. The LTZ1000 has a white noise part that about corresponds to a 100-150 K resistor. The point to possibly worry about is the low frequency noise. For the multiplying DACs this is mainly excess noise from the resistors and maybe a little from the FETs.
Because of the thermal effects I would prefer the slightly higher resistance variants, especilly if a 10 V or even slightly higher reference is used. I would consider the rather low resistance version more suitable for lower ref. voltages (e.g. 5 V).

It is hard to tell how much excess noise the ADCs have. The resistor arrays on a silicon substrate usually have low excess noise, but this is usually NiCr and not CrSi.
I see a good chance that the DAC noise would be lower than the noise of the reference also for the LF noise.
The noise data I have found so far all included the noise from the OP-amp at the output and possibly the ref. drivers.

Having separate analog and digital ground may be an issue for higher speed operation. I don't see an issue with relatively slow changing values. With only 1 GND pin (e.g. DAC8801) it should go to the analog ground as it is the return path for the DAC current. So any ground bounce here would add to the output. A seprate digital ground is nice (e.g. helps with decoupling), mainly a thing if one uses the DAC with fast changing data. With only 1 GND pin I would definitely include a series resistor / ferrite in the supply path to reduce coupling from the digial supply to the analog ground.

[CurtisSeizert]

Kleinstein,

I think the best way of dealing with the impedance issue is not to buffer the divider output but to put resistors equal to the impedance of the divider center tap at all the outputs. With regards to the higher order INL terms, they may be an issue, but most of the differential ADCs I see have third order errors being the biggest issue. This method is probably better suited for higher order terms than a string DAC. Most polynomial regression algorithms treat x, x^2, x^3... as independent variables in a multiple regression, so one quickly runs into the problem of overfitting the data set and fitting noise. I would need to review the guidelines for minimizing this problem, but larger data sets with replicates are going to help. With a 16-bit DAC, time is always going to be the limiting factor in how many points one wants to do. Algorithmically, you could imagine running a reasonable number of points (say 100), running the regression through fifth order, and re-running points with a large residual. If the residual goes down by a certain amount when you average the old data point and the new one, you can say it is noise, but if it does not, it may be that you have not captured terms to a high enough order.

I have finally finished laying out my NVM, so I will begin working on a design for this shortly, but my general philosophy is for things I am going to make one or two of, I'll spend $100 on a DAC without hesitation because I will inevitably be putting in many hours of labor as well as ordering boards, stencils, enclosures, etc. My plan was to use a DAC11001B and use an INL test of my 3458a to measure the nonlinearity of the source to be able to use it as a calibrator. The power supply will be 4S lithium cells with a LT1533 push-pull converter to generate +/- 15V as well as some other taps.  By the way, you can order DAC81001s (a 16-bit version of the 11001) directly from TI. They are about $30 in unit quantities and have the same footprint as the 18 and 20 bit versions. The noise on these is low enough that reference voltage noise is likely to be dominant.

[Kleinstein]

I like the idea if re-running those points with a large residual. When doing things manually one tends to do this also, making sure the points are real and not due to some odd effects.  This may however also be tricky as if one is not careful adds more weight to regions that show the larger initial residual.

For my setup, that is ADC noise wise comparable (to slightly better) to the 3458, but so far has only a LM399 ref. it takes quite some time for a set of voltages / point in the crive. Uusually some 10-20 minutes. It may get a little better with a better reference, as part of the averaging is needed for ref. popcorn noise that just need some averages. Even with a lower noise reference I don't see it getting much faster than some 5 minutes ( ~ 15 readings for each setting). So this would be some 200 points at most for 1 day of running the setup.  100 points sounds like a reasonable number, with possibly separate sets to check for reproduciblity and drift effects.  At least for this test there is no real need a really high resolution of highly linear DAC - 12 bits would be plenty. Of cause a different test may make good use of a better DAC.

For my ADC I was also expecting mainly an X³ term - but the data points I got so far did not support this. There seems to be more.
The even powers are usually easy to handle with the turn over test and in my case that part works really well.  So the main fit would be with only the odd powers and even with x, x^3,x^5 and x^7 there are not that many parameters to fit. A problem in the fit is that the X^5 and X^7 powers and similar higher orders still look relatively similar for most of the points. So only a small part of the data near the full scale will really make a difference. The points near zero have little effect on this more critical part of the fit.
One should still be OK to fit something like 5 or 6 parameters with suitable spaced testpoints, like more points near the ends.

Adding resistance to make all test points the same impedance may not be enough, as 2 links (input and low side) to the DMM and swiches may not have the same amount of leakage. This would especially be the case if the switches are powered from the ref./DAC unit. Also more impedance make the whole setup more sensitive to hum.
I see no problem with adding an extra buffer to the dividers - this is at least for the more high voltages like the 10 V range. The sum error does not change much when a little off the 50:50 point and the offset would be only a tiny fraction of the test voltages.
Things can be different for very low voltages, e.g. for a 100 mV range and below. There the divider can be much smaller resistance too.
Having provisions to add resistors may still be a good idea - similar it is good to have the option of an extra buffer.

[CurtisSeizert]

Interesting observations about your own test, and good point about optimizing the spacing.

Regarding the input buffers, my thought was that most low noise buffers will not do as well as an autozeroing input stage in terms of maintaining high impedance as well as low offset, but if the design to be tested did not have a high input impedance, then this could be problematic. For the design I am planning out, I plan on using something like a 19:1 divider to scale the input voltages down to 0-0.5 V, then buffering that and dividing with a three resistor string of something like 450R, 25R, and 25R. The "V_dac" would be taken from the tap between the 450 and top 25R resistors, and the center tap would be taken from between the two 25R resistors. An additional 22R at the center tap to the output would put both impedances at ~45R. I agree that at 100 mV and below, a buffer is probably not practical. In general, the choice requires one to make some assumptions about the input impedance and noise of the DUT.

I wonder if thermal tailing would be an issue if the divider for the main 10V output was, say 1k/1k. My instinct is probably not as the whole test is quite slow and the steps are fairly small, so the increase in power dissipation would not be very large. One could drive such a divider with a 3904/3906 pair without concern for biasing as you would not be crossing 0V quickly. This would keep the loop gain of the buffer amp high and isolate it from thermal EMFs.

My main motivation for using a 20-bit DAC is because measuring the INL of an ADC simultaneously allows one to measure the INL of the source, so the whole thing can serve as a voltage calibrator once the DAC's transfer function is characterized.

The MAX549x resistor networks use SiCr thin film, and these have a measured noise index of -55 dB (https://arxiv.org/pdf/2109.02448.pdf). Of the thin film types, NiCr seem to generally be the best.

[Kleinstein]

For the higher voltage the buffer would not be an issue at all. Even if not super low offset of input bias the buffer only sees the fixed divider and thus a fairly constant impedance. So any bias would only add a little offset. A little offset is not that critical: the offset does not directly add to the error sum, but effectively changes the divider to a slightly different value. The actual ratio is measured in the test and thus could be used. I see no problem if the divider ration is a little off - this only slighty increases the dependence on the ratio. If we have some 100 µV of offset and a target of 1% deviation for the divider this would still be only 10 mV for the partial voltage and 20 mV total.

Having 10 V with 1K /1K would likely run into thermal problems: that would be 5 mA and 50 mW. With such low resistors one might get away without a buffer for the center tap.
For the divider I would  more consider 10K/10K and even than there can be some thermal effect, though not sure if this would be an issue for the test.

[CurtisSeizert]

I finally got around to putting together a schematic for the single divider version. I also need a general purpose calibrator that is reasonably accurate, so that guided some of the design decisions here. The low voltage range will be good for testing INL for ranges up to 100 mV. A pdf of the interesting part is attached. The power source will be a 4S 21700 Li battery with isolated and coupled-inductor Cuk converters for the primary positive and negative rails, respectively.

[Kleinstein]

The circuit at the output of the DAC11001 looks a bit odd. As shown it is a glorified buffer amplifier with the 2 DAC internal resistors just in sereies at the feedback.

[EC8010]

I see that a great deal of thought has gone into data analysis and circuit design, but nobody has mentioned the issue of ensuring that everything is at the same temperature. For a similar problem, I fitted my parts in a sealed can, collected noise spectrum down to 20mHz, then added oil and repeated. Measured improvement as attached. Those frequencies look to be in the time scale this thread is considering. I would warn that white oil leaks through tightened threads, solved by using silicone sealant as used for assembling engines.

[CurtisSeizert]

The circuit at the output of the DAC11001 looks a bit odd. As shown it is a glorified buffer amplifier with the 2 DAC internal resistors just in sereies at the feedback.

This is the recommended configuration from the datasheet for unity gain output with matched source impedances for the buffer. The two internal resistors are in parallel as shown. The circuit is indeed just a glorified buffer, but you can have good buffers and bad ones, and I think this is a reasonable occasion for a good one.

I see that a great deal of thought has gone into data analysis and circuit design, but nobody has mentioned the issue of ensuring that everything is at the same temperature. For a similar problem, I fitted my parts in a sealed can, collected noise spectrum down to 20mHz, then added oil and repeated. Measured improvement as attached. Those frequencies look to be in the time scale this thread is considering. I would warn that white oil leaks through tightened threads, solved by using silicone sealant as used for assembling engines.

You are more dedicated than I am. Oil is a mess. I like to use the cheap Laird SMD RF shields as baffles to minimize airflow, and this works pretty well for reducing LF noise coming from thermal EMFs. My general plan here was to put the output switches reasonably far away from the other components, possibly with isolation slots. I think the TSSOP will be better than the QFN in this case because it will be possible to orient the terminals for each switch perpendicular to any thermal gradients. The lower voltage rails for the LT6018, the fact that I am using an LTZ1000A with a cathode resistor to get good TC with a lower heater setpoint, and the design of the power tree are all ultimately in service of the goal of minimizing power dissipation to make it easier to avoid excessive noise from thermal gradients. Those last two aren't shown here, but this has certainly been a design consideration.

[miro123]

I finally got around to putting together a schematic for the single divider version. I also need a general purpose calibrator that is reasonably accurate, so that guided some of the design decisions here. The low voltage range will be good for testing INL for ranges up to 100 mV. A pdf of the interesting part is attached. The power source will be a 4S 21700 Li battery with isolated and coupled-inductor Cuk converters for the primary positive and negative rails, respectively.

What is the internal DAC1101 structure?  In case of MOS SC the reference circuit should provide sink as well as source capability. The datasheet reference circuit uses sink&source buffer - no idea is this intentionally.
Sems to be SC,
1. It is logical there is no way to make such high performance device with resistors
2. datasheet shows  - THS4011 as Vref buffers- 290MHz 310V/us
3. datasheet page page 24 - "The reference pins are unbuffered; therefore, use a reference driver circuit for these pin"

[Kleinstein]

The datasheet says R2R type for the DAC. The lack of a clock (except for SPI) also sugest that this is not a SC DAC.

[CurtisSeizert]

The REF+ buffer only needs to source current and vice versa for REF-. On p. 18 of the datasheet there's a graph of the current draw from each reference pin. Thinking about this now, it might be a good move to put a resistive load between the two to increase the transconductance of the emitter followers when the load from the DAC is light. The current profile for the reference pins drops to nearly zero at the extreme codes, which seems indicative of it being an R-2R ladder rather than a string DAC for the MSBs and an R-2R ladder for the LSBs like the AD5791. The B version also implements a sample and hold deglitching filter, so in fairness, there's at least one switched cap in there.