Remote controlled DMM DCV INL tester based on voltage divider idea

[Echo88]

Heres a circuit suggestion expanding on the idea of a voltage divider being used together with ratio sum math to calculate the INL-curve of the 10V/1V/100mV ranges of a DMM, like done in a manual way here with his LTC2400 by Andreas:
https://www.eevblog.com/forum/testgear/hp34401-measurement-of-linearity/msg358682/#msg358682

Im pondering wether this method can be made good enough to characterize the INL of a 8.5 digit DMM or rather scratch the 0.1ppm realm, circumventing the need for a known linear calibrator/companion DMM.

Heres a rough description:
-very stable selectable 13V/1.3V/130mV voltage source
-connected to a voltage divider consisting of 14 thermally coupled resistors
-which are individually able to connect the binding posts to any given resistor and therefore voltage with added polarity reversal
-all situated in a milled nice alucase + inner guard case + outer earthed case
-fiber controlled via external µC/PC for lowest EMI
-battery powered for lowest EMI and avoiding CM-errors

With Python for example, it can then be used to compute an INL curve for a given DMM with the underlying math and linear fit shenanigans.

Asking for comments and criticism. 

[Andreas]

Hello,

just some annotations:

I would interleave the divider resistors RN?A - RN?H (using neighboured resistors to compensate instead of 2 halves with different temperature)
Typically the X-Capacitor at the common mode choke is larger (> factor 10) than the Y-Capacitors to ground.
I would also use another X-Capacitor on the other side of the common mode choke.
I would use the relay variant if you really have to deal with common mode disturbances.
33uF * 200 Ohm coil resistance may be a bit too low time constant to guarantee 4 ms of the "set current" especially when regarding the ~60 Ohms of the HCT374

Do you plan to do temperature control for better repeatability?

with best regards

Andreas

[CurtisSeizert]

This is an interesting idea to measure INL. I would guess Andreas used this to measure the parabolic error function because reversal is not feasible if the voltage range is positive only. I wonder if one could solve for the second order coefficient using reversal and use this method to solve for the third order coefficient. My understanding is you generate some stable voltage Va referred to GND and then check that V(a,GND) + V(ref,a) = V(ref,GND) with the goal of measuring linearity beyond what your voltage source is capable of. It does not seem critical that the voltage source be especially linear since it mostly serves to give you an x-coordinate in the nonlinearity vs input voltage that you are mapping out. Given the cost of just the photoMOS parts, you could probably just build your voltage source using an AD5791 and still come out ahead, though a less expensive DAC, as long as it is stable, should also work. You could imagine using two latching relays to switch the output voltage to check the sum or three to be able to do hands-free reversal.

With this discrete DAC, I would be a bit nervous about the SSRs and thermal EMFs contributing to low frequency noise and increasing the settling time to 0.1 ppm or less. If you are already dissipating the power of running an ADR1000 in this case, I would just put the MCU on the board and control it with an isolated USB to UART using something like an FT230 with some opto isolators. With the long integration times you will need to use to measure sub-ppm INL, a low power MCU will be of little concern for EMI as long as the layout is OK. All it will need to do is drive a DAC, a UART, and a couple GPIOs for relays. I don't think it would be necessary to scale the reference voltages for the DAC to minimize excess resistor noise if you are using something like a DAC81001 as it is 400 nV p-p with an OPA827 buffer with a 10V reference voltage. For battery powered, you could probably skip the case + shield as well, but you will want to be cognizant of the change in power dissipation that occurs over the battery discharge cycle as this can give changing offsets from thermal EMF.

[IanJ]

Nice idea, would love to see it built up and testing.

Q. How do you thermally couple 14 resistors, i.e. layout, in order to get an exact thermal affect on the all equally. With 14 I would have thought there would be an element of those towards a centre of some description.

Ian.

[Echo88]

Thanks for the feedback, ill include it in the newer revision schematic.
Andreas:
Im unsure wether it makes sense to interdigitate the RN? network (6.6Vref -> 13.2V) as the dissipation in all resistors is the same. Wont hurt to do that though, as i need to do that for the other networks anyway due to their different resistor dissipation scheme.
The CM-filter wasnt defined yet, ill include your suggestions.
The 33µF relay cap has worked great so far for these relays, so while a bit on the tight side ill continue with this value.

Temp stabilizing the case with a heater should provide added stability, when assuming that the roomtemp variation induced changing TEMF between INL tester and DMM wont completely spoil the increased stability completely.
Im still unsure wether it makes sense to add the heater or rely on alu case thermal capacity.

Curtis:
Some parts are chosen because i bought them once in quantity for quite a bit less than the new price from ebay or similar, thats why i use them here despite the contemporary new price.
In this case these are the OptoFETs, Relays, fiber-converter and i also have some suitably sized milled alu cases which once housed RF-stuff, so in this particular case i use them for best performance.
OptoFETs like PVA3054 have shown small offset voltages in the <100nV-range with low LED drive current in my measurements, though i have to test the AQW210S for this and also the TEMF settling time of single ended switching relay AGQ210A4H.
I roughly get your DAC-idea, but can you draw a schematic of it?
The changing dissipation during battery discharge is something to look out for indeed, thanks.

Ian:
The 14 resistors consisting of RN3 and RN4, while all dissipating the same power, might also be interdigitated (not yet done in the schematic) to further the thermal coupling via copper traces between them.
As these two networks will however be in separate DIP-cases they might have less statistical equal behavior (TC-ratio) than a single DIP-package with all 14 resistors in it, sitting on the same substrate. Unfortunately theres no 14 resistor network in DIP-package, which i want to avoid pcb swelling induced network instability...though that might be irrelevant given the timeframe of an INL-test...
TDP1601/1401 would be interesting, but Mouser/Digikey dont stock them.

[Kleinstein]

Like all such tests with a slow meter the test is only a spot check, testing a selction of points, never all points. There is just not enough time for all the values to check.

There are a few challanges. One is the residual error and noise of the meter under test. One sums up about equal parts and with the sum of up to 14 parts the noise and INL error also adds up.
So one needs to have assumptions on the hard INL (local errors) to make the test with the sum of many voltages work. One would need a limit for the hard INL that is quite a bit tighter than the final result.
One should complement the test with a check on the hard INL in the vincinity of the 1 V rage partial voltage. So a test to check many points the a re close by that there are no significant local INL effects, like step. Depending on the ADC to test the resistor chain idea may work or be limited by the hard INL.
As an alternative one may get away with doing the test sequence with multiple test voltages, even if only a tiy bit different, kind of avearging over possible hard INL effects.

Not sure if one really needs 14 resistors in the chain - at least for the start a shorter chain may be enough. For a start one could still have 14 resistors, but maybe only populate half the relays/switches.

The Photomos version may have problems with leakage and thermal EMF. So far I had quite good results with Photomos switches (VOR1142), but this is not guaranteed.

I would still prefer the Photomos version, though one may be able to mix, like the 4 switches for the link to the meter as electronic and the rest as relays. This way one could to the inner loop of the test faster and this way make the test faster and quieter. At least the possible offsets from these 4 switches would compensate if all 4 combinations are used in the test.

For the external ref.erence noise and drift, there is not need to be much better than the DUT. One always gets a combined noise / drift and there is little return once significant better.

[CurtisSeizert]

I attached a quick schematic using DACs after I thought about it some and had an idea of what might be a better way of doing this. By the way, I wouldn't use two AD5791s for this because it just seems like an irresponsible use of money. Maybe two DAC81001s. The various relay set positions give you V(A,GND), V(B,GND), V(A,B), and V(B,B). The last can give you an idea of the differential thermal offset between the two relays. K3 lets you invert to get negative voltages. It is not really important that your two voltages are a defined fraction of each other, just that they are stable. As such, you get some helpful flexibility for error checking here, and this could allow you to locate error peaks that are not centered in the range or centered between 0 and the upper or lower limit. With 16 bit DACs, you would get at least 1000 points on a 100mV range with Vref at ca. 13V.

Getting the required short term stability from this will still require care in design to minimize power dissipation and thermal gradients, but I think it could be done. From a thermal perspective, the LTC2756 may be a better choice as it draws much less current, but inversion of the voltage would be required, so you would need at least a -7V rail to support that. Also the LTC2758 has two channels, which is nice. I think with this general scheme, if you can get short term stability to the required level to interrogate INL at sub-ppm levels, you will be able to calculate it with fewer assumptions about placement of maxima and minima, which is worthwhile.

Edit: The schematic didn't attach.

[Kleinstein]

In principle the 2 DAC version can work, but the resistor chain may be more stable for the difference of the voltages only 1 step separate.
An advantage of the DAC version is that the voltages are low impedance, so less effect of leakage / bias currents.  For the switch/relay configuration a slightly different configuration may make more sense, with 2 separate switches to do the high/low side swiching and this way polarity choice. The 3rd optional one would than allow a separate zero level. The separate zero level could be useful for tests of the sum of 2 voltages type as than one could keep the DAC settings fixed for this - which helps with thermal and parasitic effects.


For switching one does not need isolation. So instead of the Photo-mos switches one could as well use CMOS switch chips, if one is a bit careful with ESD. This could especially simplify things for a version with only 8 resistors, because there are good 8:1 mux chips available.
If the output resistance of the resistor chain is an issue (e.g. high bias from the DUT and switch leakage), one could have separate buffers for the taps. The offset of the buffers could be treated as part of the ref. voltage. With 7 - 12 taps this is still managable.

[guenthert]

I think this is in spirit what [1] hints at (but doesn't elaborate on).  There commercially available automatic switch systems (scanner) with low thermal EMF were used (Dataproof?) .

Since you need only short term stability, some money could be saved by substituting the ADR1000 for a cheaper reference.  Or leave it out and allow for an external ~7V reference one might posses already.


[1] https://www.nist.gov/system/files/documents/calibrations/im-34-2a.pdf

[Kleinstein]

For the reference one still needs low noise and good stability over the range of some 10-30 seconds for the simple sum of 2 voltages test, and maybe 10s of  minutes for the full chain von 1 V steps.
One may get away with a different solution, but it is still not easy. A couple (e.g. 5 x 2.5 V) of LTC6655 are also not cheap and still a bit noisy.  A JFET based ref. may work, but needs tinkering / trimming of the resistors. A ADR1000 / LTZ1000 with not especially expensive resistors could still be sensible option, just for low noise.
At the very low cost end, a set of thermally well insulated batteries can do the trick (especially for the faster tests like turn over and sum of 2 voltages), if one does a check over multiple repeats and maybe simple drift correction.

For the remote control it would be good to have the automation for a single INL test sequency, so that this can run reasonable fast and repeated over multiple cycles. This helps with the reference drift and very low frequency noise. For different test types or ranges one could likely still get away with manual switching / jumpers. 

[Echo88]

Yes, the ADR/LTZ1000 was chosen as the lowest shortterm drift and noise reference. But maybe some paralleled LTC6655(-LN) would be more cost efficient/achieve better specs in general.
Thermally stabilized batteries should provide lower noise, but i have no experience just how stable you can get them and therefore didnt go that route.
Did anyone do measurements on CMOS analog switches for offset voltages? Id assume they should be very low, especially due to the low switch quiescent current.

[Kleinstein]

I have tried batteries for a INL test, however only for the relatively fast parts with only 4 readings in the loop (some 20 s for the loop). It works when there is interpolation in time to correct for a linear drift rate. When really stable in temperature it may also work without. I don't consider it very practical for much slower tests.

Some LTC6655 may be a little more cost effective. 2 x LTC665 combined in series or parallel may reach a comparable noise level (relative to the voltage), if one can belief the DS numbers. One uncertainty with the DS values is the exact filter used - some cut off more than others. So the frequency ranges are not all the same approximation of the standard 0.1-10 Hz range.
A FAIK the LTC6655LN version only adds RC filtering and this would not really help much with the test, as most DMMs / high resolution ADCs are relative slow anyway. Still some (with 1 PLC classical AZ cycle) react to noise around 25 Hz. With a large capacitor the LN version may just help here. Similar filtering may as well be external also with other reference. If it is relevant depends on the DMM.

Also ADR1399 may be feasable - 2 combined could also reach a similar noise level.

I have used CMOS mux chips, especially DG408 quite a bit. I don't have numbers on the absolute offset, but different channels usually agree quite well, though not perfect and the offset seems to be quite stable over time. Also with intentional warming they don't seem to be very sensitive - the more tricky parts are some resisors that show thermal EMF. So they are likely better than most photomos switches. As far as I see it the string type DAC would only need stable offsets, not a low offset.

[CurtisSeizert]

I was thinking about this some more, and I believe there is a simpler way to accomplish the goal of determining the higher order transfer function coefficients. You just feed a resistor divider with a stable voltage source, say from a DAC. The divider should have a reasonably consistent ratio over the voltage range in question, at least with the math I did, but there may be a way of working it out so you can compensate for voltage coefficients. So with the resistor divider, we have three nodes, the DAC output (DAC), the center tap of the divider (CT), and ground. So you can connect these nodes to the front panel with relays as in OP's schematic. The procedure is as follows.

1. Call the ADC transfer function Y(x) = a0 + a1*x + a2*x^2 + a3*x^3 + a4 * x^4 ...
2. For each DAC voltage you measure V(CT,GND) + V(DAC,CT) - V(DAC,GND) to get your error function. For a reasonably accurate ADC, x in the transfer function can just be V(DAC,GND).
3. Run a polynomial fit of the error function to get the coefficients delta(x) = c0 + c2 * x^2 + c3 * x^3 + c4 * x^4  ... (the linear term should be insignificant)
4. Calculate the divider ratio as b = V(CT,GND)/(V(CT,GND) + V(DAC,CT)).
5. The relationships between the coefficients are
     a0 = c0
     a2 = c2/(-2b + 2b^2)
     a3 = c3/(-3b + 3b^2)
     a4 = c4/(-4b + 6b^2 -3b^3 + 2b^4)
     a5 = c5/(-5b + 10b^2 - 10b^3 + 5b^4)

In practice, you can add reversal to extend the voltage range and/or check the even order coefficients. The system will be most forgiving around a 1:1 ratio, as each of the functions of the ratio b (in step 5) has a first derivative of 0 at b = 0.5. On the hardware side, I believe this will be easier to implement than a string DAC using discrete resistors because only relays are necessary for switching the voltages (minimally two, three DPDT for reversal), and temperature homogeneity of a monolithic divider is going to be much easier to achieve than it is with a handful of discretes. The primary requirement for the voltage source (i.e. the voltage reference and the DAC) is low noise and reasonable short term stability.

I will probably make one of these (with some modifications for low voltages) for testing the nanovoltmeter I am working on. I will probably just use an ADR1000 reference as I have a handful of reference modules that use these sitting around.

[Echo88]

Thanks for the input, im curious about your DAC based nV-meter variant results. 
I havent yet thought about the necessary math behind the string divider yet, as i was busy doing the final schematic and layout corrections. Maybe this paper also gives some ideas regarding the math: https://download.flukecal.com/pub/literature/Automatic_Linearity_Calibration.pdf
Meanwhile i settled for MUX36S16 as voltage tap switches instead of OptoFETs/Relays for size reasons and since im expecting neglegible voltage offset contribution from them so they should be about equal in performance to AQW210S for example.
Ill test the voltage offset of the MUX36S16 with another test pcb and my 34420A beforehand.

[CurtisSeizert]

I'll post a schematic when I get there. I was looking at switches for the string DAC and came to the same conclusion as you about the best switch for the job.

[Kleinstein]

Measuing the both halfs of the divider is a good idea. In the test loop one should add a 4 th offset measurement as (V(CT,CT). This would eliminate offsets of the meter and also the swiched.
As much of the effort is with the external reference and DAC it would likely make sense to have at least 2 divider ratios (e.g. b = 1/2 and 1/3), as an extra check.
Ideally one should run the test several times to reduce the errors from ref. drift and noise. The drift part can be reduces with interpolation in time (average on values before and after in the sequence).
Chances are one would not need a LTZ / ADR1000 grade ref., a ADR1399 should be good enough. It mainly needs a few more repeats if the references are a bit noisy.

[Kleinstein]

I looked a bit more at the test with the divider and different total voltages. The divider ratio b is not very critical.  The initial sum of V(CT,GND) + V(DAC,CT) - V(DAC,GND)  already reduced the required resolution and required accuracy for the further math.  These sums are already much smaller (e.g. about the size of the INL error). The factors in the conversion from the C0...Cn polnynom to the a0..an form depend on the divider ratio b, but not very much. Even if there is an error in the percent range this would be a percent error relative to the INL - unless one has a huge error and wants to correct the error one does not really care wether the INL is at 1 ppm or 1.1 ppm.  So the divider should not be critical at all. If the meter under test is relativey low in impedance one could even have a fixed buffer at the divider, as long as the offset there is not too large (e.g. < 5 % of the voltage). The error to the divider is still moderate and the first sum already compensates most of it.

For the accuracy the test is not so much relying on a fixed divider. The main point is that the sum of 2 voltages in series adds up and thus no change to the voltages when switching the configuration.
The linearity and stability of the divider should not be an issue. The point is more that loading the divider (switching different links to CT) does not chance the voltage. So a buffer for the divider center (even if with some offset) would be a point to consider.

Chances are that the even powers are easier tested with the simpler turn over test, comparing the 2 polarities.

[CurtisSeizert]

Those points are all consistent with the observations I made when I was working out the math. The divider ratio is indeed not that critical, but the impact of divider ratio inaccuracies is least with a ratio of 1:1. An issue to consider with the buffer is the linearity of the buffer itself if the goal is to measure nonlinear gain terms at sub-ppm accuracy. One way around this would be to tap off the input of the buffer and the output and measure Vos with the DUT at the test voltages as part of the test. This may be unnecessary with an AZ op amp if the CMRR is high enough or is predominantly linear. Another potential solution would be to add the equivalent output impedance of the divider at the DAC and GND outputs.

The implementation I had considered would use the output switching I had in the schematic I posted before, and I agree that it would be good to get V(CT,CT) at each step of the test to mostly cancel thermal offsets. I had also planned to incorporate reversal because being able to isolate the even order coefficients could give better accuracy. It would be interesting to write a quick python script (or even just use excel) with some RNG-based noise to get an idea of how accurately one could determine the coefficients.

I would probably use a DAC11001A and either an ADR1000 or an ADR1399 because I have those parts on hand. I believe all the TI DACs in that series have interchangeable pinouts, so the 16- or 18-bit versions could fit the same board and reduce the BOM cost. With either reference, a battery power supply boosted with an LT1533 + LDOs could be a good way to keep power dissipation consistent as the batteries discharge.

[Kleinstein]

The extra buffer for the divider would naturally be powered from the reference side. So the CMRR would not be really important. An offset there corresponds to a small error in the divider ratio and is thus not that critical (sepcially for higher voltage ranges). Especially at 1:1 the exact ratio is sopposed to be not that important, even if the ratio changes slightly over time and thus diffent test votlages.

The INL test from the sum of 2 voltages only need short time stability for a run of the 3 or 4 measurements (in may case this are some 20 seconds - with relay switching one may want it a bit slower).
It depends on the system to test, but I would not expect the normal random noise to be the limiting factor. There is always the chance to let the system run for quite some time, if it is automated. The white noise part should be relatively easy, though it gets more important for lower voltages. The low frequency noise from the references and maybe thermal fluctuations is more the limiting factor.

Another point could be the hard INL of the DUT - so more local deviations in the INL curve that are not well described by a polynominal. For a SAR type ADC this would be steps of high value bits and for a SD and similar ADC this can be idle tone / special feedback patterns. To reduce the effect it would need quite a few test points. So well more than the min. number needed to fit something like a 6th order poylnominal for the INL. It is anyway a good question on what polynominal order to use for the assumed soft INL part.

[miro123]

1. Call the ADC transfer function Y(x) = a0 + a1*x + a2*x^2 + a3*x^3 + a4 * x^4 ...
2. For each DAC voltage you measure V(CT,GND) + V(DAC,CT) - V(DAC,GND) to get your error function. For a reasonably accurate ADC, x in the transfer function can just be V(DAC,GND).
3. Run a polynomial fit of the error function to get the coefficients delta(x) = c0 + c2 * x^2 + c3 * x^3 + c4 * x^4  ... (the linear term should be insignificant)
4. Calculate the divider ratio as b = V(CT,GND)/(V(CT,GND) + V(DAC,CT)).
5. The relationships between the coefficients are
     a0 = c0
     a2 = c2/(-2b + 2b^2)
     a3 = c3/(-3b + 3b^2)
     a4 = c4/(-4b + 6b^2 -3b^3 + 2b^4)
     a5 = c5/(-5b + 10b^2 - 10b^3 + 5b^4)

#4. Are you running to chicken en eggs problem?
I did not to the error calculation but my "feeling" is that small error in B calculation introduce huge error in a0....a5 calculation - it is 4-th order polynomial for a5
#4 I also expect that b varies with V(CT) since you are running divider at different power - maybe fake measurements due to thermal EMFs.
Maybe running pythhon script with error estimation /sensitivity calculation/ can help to validate your solution

[Kleinstein]

The sensitivity to changes in the divider ratio is really small, especially of near b= 0.5.  The polynomina in b are only effecting the scaling factors to convert from one decription to the other. So b does not need to be stable / accurate to the ppm level - just the percent level is good enough and it would hardly matter if b changes a little with the voltage (e.g. with thermal EMF or an offest from an extra buffer for the center tap). The need for ppm level (or whatever resolution is needed for the INL) stability and "accuracy" is when getting the error function, as the sum with the 3 or 4 parts. Here it can be starting with up to some 10 V and about getting the values to the 1 µV and ideally better resolution and low noise and repeatablity. With a reasonable good ADC/DVM the sum will be in the µV maybe 10s of µV range.
The relative accuracy for the C0..C5  would not be great to start with and having the fators depending on b to be a little off would not be an issue. It takes a rather poor divider to get changes in b of more than 0.1%.

I am a bit surprized that the conversion from the error function to the INL polynomina is so simple and well behaved. I have not checked the calculation though.  With b = 0.5 the factors are at some 2 , 1.33, 1.33 and 1.066 and thus not very large.  The even powers are anyway likely better measured with a slightly simpler turn over test and one may also inclode a 6th power there.
For the odd power there are than a3 and a5 left, so only 2 parameters to be really meaured with this series of tests.

[miro123]

I agree that C part has less influence in total uncertainty.
I find this idea great but still many thinks are not clear yet.
1. I don't have the full picture of uncertainty even using the idealized models.
2. I think that CT buff cannot be powered from DAC  out.
3. CT buffer CMMR is the smalest issue the problem is that Ib varies with common mode and  Ib also depend from opamp supply voltage
4. But here are many other fundamental questions - what does it mean the error function - Let assume 0,5 divider - ErrorFunct = 2* Error(Udac/2)- Err(Udac) - This function look like regression polynomial, isn't it?
Assuming Udac- 5V that ErrorFunct(5) = U(~2,5)+ U(~2,5) - U(~5)
Later on ErrorFunct(2,5) = U(~1,25)+ U(~1,25) - U(~2,5)
and so on
Another question is what does error function phisicaly represent - error at 5V, at 2.5V or combined?
My point is that It requires calculation the total uncertainty of proposed solution. I see a plenty of error sources - without calculation is hard to say what for accuracy are you gonna achieve.

[Kleinstein]

In the simple form the test does not need a buffer at the center of the divider. The problem here is however that a bias (and common mode leakage) current from the DUT can cause an error that depends on the switch settings to choose which voltage is measured. A buffer at the CT would essentially eliminate this problem as the buffer has not problem driving a current in the nA range. The buffer can add an offset error (directly and via bias and divider impedance), but this error is essentially fixed, at least for the test at one voltage.

There is no problem to power the buffer from the DAC = external tester side, as the CM voltage is well within the supply there. The main point of the buffer is that it is not good to have a variable load there and thus a buffer powered from the DUT side is not good.

The tests with the 3(4) readings that should ideally sum up to zero gives a mix of the INL at  3 points , with the 0.5 divider ratio 2 of them fall together and thus only 2 INL points mixed.
One could see the test as taking the reading at half the reading and than compare the extrapolation to the full value with the reading at the full voltage.
For the test with the full-scale voltage one has a easier interpretation, as the common definition is to have the INL curve at zero for the ends of the range. So INL(FS) = 0 per definiton and one gets  Err(FS)  = 2 x INL(FS/2) for the test. In theory one could than do a 2nd test at Udac = FS/2 and this way get INL(FS/4) = 0.5 * ( ERR(FS/2) - INL(FS/2)) =  0.5 * ERR(FS/2) - 0.25*ERR(FS)

A weak point of the analysis with the polynominal fit is the assumption that the INL is a rather smooth curve and the polynominal approximation is good. It depends on the DUT if this is really the case. For an integrating ADC this may well work, with a SAR type ADC this may not work that well as the INL curve is usally a more stepped function. Even with  an integrating ADC there can also be more lokal error, e.g. from idle tones.

[miro123]

Idea is interesting.
Simulation results are ok. I gonna breadborad one and just for fun I will calibrate one of my ADS1256/PGA280  boards.
Instead of resistive divider I will use MAX5387 because I have some of them in the drawer.

[Kleinstein]

I ran a few tests on the sum of 2 voltages test with my DIY DMM. The switching part is already part of the DMM with 2 inputs and 2 low sides to choose from.  This are effectively 2 double through switches to set the 4 parts of the test. In my case a 0 V reading (to get the offset), some 8.76 V and some 9.24 V from a 9 V block each and finally a 18 V reading as the sum of the 2 voltages.
The readings are 7 readings of 32x1 PLC and than 1 reading that is effected by the switching and droped later for each of the steps. Together a cycle needs some 21 seconds. To allow compensation for the drift 2 cycles are combined and the values are interpolated to a common time.  For a fully automated test one would need the controllable source instead of the 2 x 9 V.

The 2nd attachment shows the more raw data. To get all 4 readings in 1 plot only the last 3 digits and thus a 100 µV wrap around (modulo) is shown.
One can see quite some drift (~ 50 µV for the sum) is present as the batteries are low noise, but not low TC or long term stable. the drift make the interpolation in time mecessary.
The 1nd graph shows the calculated residual for the  summation (0+18-9-9): there are quite a few outliers, but many of the points are around 7.7 µV.
Some of the outliers are likely from popcorn noise in the DMM reference (LM399). Similar errors from the external votlages are also possible.

To get a reasonable stable result it needs quite a bit of averaging / not as much as used here, but some 20 repeats for the cycle seem to be a good idea. So this would be some 15 minutes for 1 point to the curve. Of cause the time needed depends on the ADC / DMM to test. For a reasonable polynominal fit it would need maybe 10 points at least, better quite a few more.