Remote controlled DMM DCV INL tester based on voltage divider idea

[Echo88]

Heres a circuit suggestion expanding on the idea of a voltage divider being used together with ratio sum math to calculate the INL-curve of the 10V/1V/100mV ranges of a DMM, like done in a manual way here with his LTC2400 by Andreas:
https://www.eevblog.com/forum/testgear/hp34401-measurement-of-linearity/msg358682/#msg358682

Im pondering wether this method can be made good enough to characterize the INL of a 8.5 digit DMM or rather scratch the 0.1ppm realm, circumventing the need for a known linear calibrator/companion DMM.

Heres a rough description:
-very stable selectable 13V/1.3V/130mV voltage source
-connected to a voltage divider consisting of 14 thermally coupled resistors
-which are individually able to connect the binding posts to any given resistor and therefore voltage with added polarity reversal
-all situated in a milled nice alucase + inner guard case + outer earthed case
-fiber controlled via external µC/PC for lowest EMI
-battery powered for lowest EMI and avoiding CM-errors

With Python for example, it can then be used to compute an INL curve for a given DMM with the underlying math and linear fit shenanigans.

Asking for comments and criticism. 

[Andreas]

Hello,

just some annotations:

I would interleave the divider resistors RN?A - RN?H (using neighboured resistors to compensate instead of 2 halves with different temperature)
Typically the X-Capacitor at the common mode choke is larger (> factor 10) than the Y-Capacitors to ground.
I would also use another X-Capacitor on the other side of the common mode choke.
I would use the relay variant if you really have to deal with common mode disturbances.
33uF * 200 Ohm coil resistance may be a bit too low time constant to guarantee 4 ms of the "set current" especially when regarding the ~60 Ohms of the HCT374

Do you plan to do temperature control for better repeatability?

with best regards

Andreas

[CurtisSeizert]

This is an interesting idea to measure INL. I would guess Andreas used this to measure the parabolic error function because reversal is not feasible if the voltage range is positive only. I wonder if one could solve for the second order coefficient using reversal and use this method to solve for the third order coefficient. My understanding is you generate some stable voltage Va referred to GND and then check that V(a,GND) + V(ref,a) = V(ref,GND) with the goal of measuring linearity beyond what your voltage source is capable of. It does not seem critical that the voltage source be especially linear since it mostly serves to give you an x-coordinate in the nonlinearity vs input voltage that you are mapping out. Given the cost of just the photoMOS parts, you could probably just build your voltage source using an AD5791 and still come out ahead, though a less expensive DAC, as long as it is stable, should also work. You could imagine using two latching relays to switch the output voltage to check the sum or three to be able to do hands-free reversal.

With this discrete DAC, I would be a bit nervous about the SSRs and thermal EMFs contributing to low frequency noise and increasing the settling time to 0.1 ppm or less. If you are already dissipating the power of running an ADR1000 in this case, I would just put the MCU on the board and control it with an isolated USB to UART using something like an FT230 with some opto isolators. With the long integration times you will need to use to measure sub-ppm INL, a low power MCU will be of little concern for EMI as long as the layout is OK. All it will need to do is drive a DAC, a UART, and a couple GPIOs for relays. I don't think it would be necessary to scale the reference voltages for the DAC to minimize excess resistor noise if you are using something like a DAC81001 as it is 400 nV p-p with an OPA827 buffer with a 10V reference voltage. For battery powered, you could probably skip the case + shield as well, but you will want to be cognizant of the change in power dissipation that occurs over the battery discharge cycle as this can give changing offsets from thermal EMF.

[IanJ]

Nice idea, would love to see it built up and testing.

Q. How do you thermally couple 14 resistors, i.e. layout, in order to get an exact thermal affect on the all equally. With 14 I would have thought there would be an element of those towards a centre of some description.

Ian.

[Echo88]

Thanks for the feedback, ill include it in the newer revision schematic.
Andreas:
Im unsure wether it makes sense to interdigitate the RN? network (6.6Vref -> 13.2V) as the dissipation in all resistors is the same. Wont hurt to do that though, as i need to do that for the other networks anyway due to their different resistor dissipation scheme.
The CM-filter wasnt defined yet, ill include your suggestions.
The 33µF relay cap has worked great so far for these relays, so while a bit on the tight side ill continue with this value.

Temp stabilizing the case with a heater should provide added stability, when assuming that the roomtemp variation induced changing TEMF between INL tester and DMM wont completely spoil the increased stability completely.
Im still unsure wether it makes sense to add the heater or rely on alu case thermal capacity.

Curtis:
Some parts are chosen because i bought them once in quantity for quite a bit less than the new price from ebay or similar, thats why i use them here despite the contemporary new price.
In this case these are the OptoFETs, Relays, fiber-converter and i also have some suitably sized milled alu cases which once housed RF-stuff, so in this particular case i use them for best performance.
OptoFETs like PVA3054 have shown small offset voltages in the <100nV-range with low LED drive current in my measurements, though i have to test the AQW210S for this and also the TEMF settling time of single ended switching relay AGQ210A4H.
I roughly get your DAC-idea, but can you draw a schematic of it?
The changing dissipation during battery discharge is something to look out for indeed, thanks.

Ian:
The 14 resistors consisting of RN3 and RN4, while all dissipating the same power, might also be interdigitated (not yet done in the schematic) to further the thermal coupling via copper traces between them.
As these two networks will however be in separate DIP-cases they might have less statistical equal behavior (TC-ratio) than a single DIP-package with all 14 resistors in it, sitting on the same substrate. Unfortunately theres no 14 resistor network in DIP-package, which i want to avoid pcb swelling induced network instability...though that might be irrelevant given the timeframe of an INL-test...
TDP1601/1401 would be interesting, but Mouser/Digikey dont stock them.

[Kleinstein]

Like all such tests with a slow meter the test is only a spot check, testing a selction of points, never all points. There is just not enough time for all the values to check.

There are a few challanges. One is the residual error and noise of the meter under test. One sums up about equal parts and with the sum of up to 14 parts the noise and INL error also adds up.
So one needs to have assumptions on the hard INL (local errors) to make the test with the sum of many voltages work. One would need a limit for the hard INL that is quite a bit tighter than the final result.
One should complement the test with a check on the hard INL in the vincinity of the 1 V rage partial voltage. So a test to check many points the a re close by that there are no significant local INL effects, like step. Depending on the ADC to test the resistor chain idea may work or be limited by the hard INL.
As an alternative one may get away with doing the test sequence with multiple test voltages, even if only a tiy bit different, kind of avearging over possible hard INL effects.

Not sure if one really needs 14 resistors in the chain - at least for the start a shorter chain may be enough. For a start one could still have 14 resistors, but maybe only populate half the relays/switches.

The Photomos version may have problems with leakage and thermal EMF. So far I had quite good results with Photomos switches (VOR1142), but this is not guaranteed.

I would still prefer the Photomos version, though one may be able to mix, like the 4 switches for the link to the meter as electronic and the rest as relays. This way one could to the inner loop of the test faster and this way make the test faster and quieter. At least the possible offsets from these 4 switches would compensate if all 4 combinations are used in the test.

For the external ref.erence noise and drift, there is not need to be much better than the DUT. One always gets a combined noise / drift and there is little return once significant better.

[CurtisSeizert]

I attached a quick schematic using DACs after I thought about it some and had an idea of what might be a better way of doing this. By the way, I wouldn't use two AD5791s for this because it just seems like an irresponsible use of money. Maybe two DAC81001s. The various relay set positions give you V(A,GND), V(B,GND), V(A,B), and V(B,B). The last can give you an idea of the differential thermal offset between the two relays. K3 lets you invert to get negative voltages. It is not really important that your two voltages are a defined fraction of each other, just that they are stable. As such, you get some helpful flexibility for error checking here, and this could allow you to locate error peaks that are not centered in the range or centered between 0 and the upper or lower limit. With 16 bit DACs, you would get at least 1000 points on a 100mV range with Vref at ca. 13V.

Getting the required short term stability from this will still require care in design to minimize power dissipation and thermal gradients, but I think it could be done. From a thermal perspective, the LTC2756 may be a better choice as it draws much less current, but inversion of the voltage would be required, so you would need at least a -7V rail to support that. Also the LTC2758 has two channels, which is nice. I think with this general scheme, if you can get short term stability to the required level to interrogate INL at sub-ppm levels, you will be able to calculate it with fewer assumptions about placement of maxima and minima, which is worthwhile.

Edit: The schematic didn't attach.

[Kleinstein]

In principle the 2 DAC version can work, but the resistor chain may be more stable for the difference of the voltages only 1 step separate.
An advantage of the DAC version is that the voltages are low impedance, so less effect of leakage / bias currents.  For the switch/relay configuration a slightly different configuration may make more sense, with 2 separate switches to do the high/low side swiching and this way polarity choice. The 3rd optional one would than allow a separate zero level. The separate zero level could be useful for tests of the sum of 2 voltages type as than one could keep the DAC settings fixed for this - which helps with thermal and parasitic effects.


For switching one does not need isolation. So instead of the Photo-mos switches one could as well use CMOS switch chips, if one is a bit careful with ESD. This could especially simplify things for a version with only 8 resistors, because there are good 8:1 mux chips available.
If the output resistance of the resistor chain is an issue (e.g. high bias from the DUT and switch leakage), one could have separate buffers for the taps. The offset of the buffers could be treated as part of the ref. voltage. With 7 - 12 taps this is still managable.

[guenthert]

I think this is in spirit what [1] hints at (but doesn't elaborate on).  There commercially available automatic switch systems (scanner) with low thermal EMF were used (Dataproof?) .

Since you need only short term stability, some money could be saved by substituting the ADR1000 for a cheaper reference.  Or leave it out and allow for an external ~7V reference one might posses already.


[1] https://www.nist.gov/system/files/documents/calibrations/im-34-2a.pdf

[Kleinstein]

For the reference one still needs low noise and good stability over the range of some 10-30 seconds for the simple sum of 2 voltages test, and maybe 10s of  minutes for the full chain von 1 V steps.
One may get away with a different solution, but it is still not easy. A couple (e.g. 5 x 2.5 V) of LTC6655 are also not cheap and still a bit noisy.  A JFET based ref. may work, but needs tinkering / trimming of the resistors. A ADR1000 / LTZ1000 with not especially expensive resistors could still be sensible option, just for low noise.
At the very low cost end, a set of thermally well insulated batteries can do the trick (especially for the faster tests like turn over and sum of 2 voltages), if one does a check over multiple repeats and maybe simple drift correction.

For the remote control it would be good to have the automation for a single INL test sequency, so that this can run reasonable fast and repeated over multiple cycles. This helps with the reference drift and very low frequency noise. For different test types or ranges one could likely still get away with manual switching / jumpers. 

[Echo88]

Yes, the ADR/LTZ1000 was chosen as the lowest shortterm drift and noise reference. But maybe some paralleled LTC6655(-LN) would be more cost efficient/achieve better specs in general.
Thermally stabilized batteries should provide lower noise, but i have no experience just how stable you can get them and therefore didnt go that route.
Did anyone do measurements on CMOS analog switches for offset voltages? Id assume they should be very low, especially due to the low switch quiescent current.

[Kleinstein]

I have tried batteries for a INL test, however only for the relatively fast parts with only 4 readings in the loop (some 20 s for the loop). It works when there is interpolation in time to correct for a linear drift rate. When really stable in temperature it may also work without. I don't consider it very practical for much slower tests.

Some LTC6655 may be a little more cost effective. 2 x LTC665 combined in series or parallel may reach a comparable noise level (relative to the voltage), if one can belief the DS numbers. One uncertainty with the DS values is the exact filter used - some cut off more than others. So the frequency ranges are not all the same approximation of the standard 0.1-10 Hz range.
A FAIK the LTC6655LN version only adds RC filtering and this would not really help much with the test, as most DMMs / high resolution ADCs are relative slow anyway. Still some (with 1 PLC classical AZ cycle) react to noise around 25 Hz. With a large capacitor the LN version may just help here. Similar filtering may as well be external also with other reference. If it is relevant depends on the DMM.

Also ADR1399 may be feasable - 2 combined could also reach a similar noise level.

I have used CMOS mux chips, especially DG408 quite a bit. I don't have numbers on the absolute offset, but different channels usually agree quite well, though not perfect and the offset seems to be quite stable over time. Also with intentional warming they don't seem to be very sensitive - the more tricky parts are some resisors that show thermal EMF. So they are likely better than most photomos switches. As far as I see it the string type DAC would only need stable offsets, not a low offset.

[CurtisSeizert]

I was thinking about this some more, and I believe there is a simpler way to accomplish the goal of determining the higher order transfer function coefficients. You just feed a resistor divider with a stable voltage source, say from a DAC. The divider should have a reasonably consistent ratio over the voltage range in question, at least with the math I did, but there may be a way of working it out so you can compensate for voltage coefficients. So with the resistor divider, we have three nodes, the DAC output (DAC), the center tap of the divider (CT), and ground. So you can connect these nodes to the front panel with relays as in OP's schematic. The procedure is as follows.

1. Call the ADC transfer function Y(x) = a0 + a1*x + a2*x^2 + a3*x^3 + a4 * x^4 ...
2. For each DAC voltage you measure V(CT,GND) + V(DAC,CT) - V(DAC,GND) to get your error function. For a reasonably accurate ADC, x in the transfer function can just be V(DAC,GND).
3. Run a polynomial fit of the error function to get the coefficients delta(x) = c0 + c2 * x^2 + c3 * x^3 + c4 * x^4  ... (the linear term should be insignificant)
4. Calculate the divider ratio as b = V(CT,GND)/(V(CT,GND) + V(DAC,CT)).
5. The relationships between the coefficients are
     a0 = c0
     a2 = c2/(-2b + 2b^2)
     a3 = c3/(-3b + 3b^2)
     a4 = c4/(-4b + 6b^2 -3b^3 + 2b^4)
     a5 = c5/(-5b + 10b^2 - 10b^3 + 5b^4)

In practice, you can add reversal to extend the voltage range and/or check the even order coefficients. The system will be most forgiving around a 1:1 ratio, as each of the functions of the ratio b (in step 5) has a first derivative of 0 at b = 0.5. On the hardware side, I believe this will be easier to implement than a string DAC using discrete resistors because only relays are necessary for switching the voltages (minimally two, three DPDT for reversal), and temperature homogeneity of a monolithic divider is going to be much easier to achieve than it is with a handful of discretes. The primary requirement for the voltage source (i.e. the voltage reference and the DAC) is low noise and reasonable short term stability.

I will probably make one of these (with some modifications for low voltages) for testing the nanovoltmeter I am working on. I will probably just use an ADR1000 reference as I have a handful of reference modules that use these sitting around.

[Echo88]

Thanks for the input, im curious about your DAC based nV-meter variant results. 
I havent yet thought about the necessary math behind the string divider yet, as i was busy doing the final schematic and layout corrections. Maybe this paper also gives some ideas regarding the math: https://download.flukecal.com/pub/literature/Automatic_Linearity_Calibration.pdf
Meanwhile i settled for MUX36S16 as voltage tap switches instead of OptoFETs/Relays for size reasons and since im expecting neglegible voltage offset contribution from them so they should be about equal in performance to AQW210S for example.
Ill test the voltage offset of the MUX36S16 with another test pcb and my 34420A beforehand.

[CurtisSeizert]

I'll post a schematic when I get there. I was looking at switches for the string DAC and came to the same conclusion as you about the best switch for the job.

[Kleinstein]

Measuing the both halfs of the divider is a good idea. In the test loop one should add a 4 th offset measurement as (V(CT,CT). This would eliminate offsets of the meter and also the swiched.
As much of the effort is with the external reference and DAC it would likely make sense to have at least 2 divider ratios (e.g. b = 1/2 and 1/3), as an extra check.
Ideally one should run the test several times to reduce the errors from ref. drift and noise. The drift part can be reduces with interpolation in time (average on values before and after in the sequence).
Chances are one would not need a LTZ / ADR1000 grade ref., a ADR1399 should be good enough. It mainly needs a few more repeats if the references are a bit noisy.

[Kleinstein]

I looked a bit more at the test with the divider and different total voltages. The divider ratio b is not very critical.  The initial sum of V(CT,GND) + V(DAC,CT) - V(DAC,GND)  already reduced the required resolution and required accuracy for the further math.  These sums are already much smaller (e.g. about the size of the INL error). The factors in the conversion from the C0...Cn polnynom to the a0..an form depend on the divider ratio b, but not very much. Even if there is an error in the percent range this would be a percent error relative to the INL - unless one has a huge error and wants to correct the error one does not really care wether the INL is at 1 ppm or 1.1 ppm.  So the divider should not be critical at all. If the meter under test is relativey low in impedance one could even have a fixed buffer at the divider, as long as the offset there is not too large (e.g. < 5 % of the voltage). The error to the divider is still moderate and the first sum already compensates most of it.

For the accuracy the test is not so much relying on a fixed divider. The main point is that the sum of 2 voltages in series adds up and thus no change to the voltages when switching the configuration.
The linearity and stability of the divider should not be an issue. The point is more that loading the divider (switching different links to CT) does not chance the voltage. So a buffer for the divider center (even if with some offset) would be a point to consider.

Chances are that the even powers are easier tested with the simpler turn over test, comparing the 2 polarities.

[CurtisSeizert]

Those points are all consistent with the observations I made when I was working out the math. The divider ratio is indeed not that critical, but the impact of divider ratio inaccuracies is least with a ratio of 1:1. An issue to consider with the buffer is the linearity of the buffer itself if the goal is to measure nonlinear gain terms at sub-ppm accuracy. One way around this would be to tap off the input of the buffer and the output and measure Vos with the DUT at the test voltages as part of the test. This may be unnecessary with an AZ op amp if the CMRR is high enough or is predominantly linear. Another potential solution would be to add the equivalent output impedance of the divider at the DAC and GND outputs.

The implementation I had considered would use the output switching I had in the schematic I posted before, and I agree that it would be good to get V(CT,CT) at each step of the test to mostly cancel thermal offsets. I had also planned to incorporate reversal because being able to isolate the even order coefficients could give better accuracy. It would be interesting to write a quick python script (or even just use excel) with some RNG-based noise to get an idea of how accurately one could determine the coefficients.

I would probably use a DAC11001A and either an ADR1000 or an ADR1399 because I have those parts on hand. I believe all the TI DACs in that series have interchangeable pinouts, so the 16- or 18-bit versions could fit the same board and reduce the BOM cost. With either reference, a battery power supply boosted with an LT1533 + LDOs could be a good way to keep power dissipation consistent as the batteries discharge.

[Kleinstein]

The extra buffer for the divider would naturally be powered from the reference side. So the CMRR would not be really important. An offset there corresponds to a small error in the divider ratio and is thus not that critical (sepcially for higher voltage ranges). Especially at 1:1 the exact ratio is sopposed to be not that important, even if the ratio changes slightly over time and thus diffent test votlages.

The INL test from the sum of 2 voltages only need short time stability for a run of the 3 or 4 measurements (in may case this are some 20 seconds - with relay switching one may want it a bit slower).
It depends on the system to test, but I would not expect the normal random noise to be the limiting factor. There is always the chance to let the system run for quite some time, if it is automated. The white noise part should be relatively easy, though it gets more important for lower voltages. The low frequency noise from the references and maybe thermal fluctuations is more the limiting factor.

Another point could be the hard INL of the DUT - so more local deviations in the INL curve that are not well described by a polynominal. For a SAR type ADC this would be steps of high value bits and for a SD and similar ADC this can be idle tone / special feedback patterns. To reduce the effect it would need quite a few test points. So well more than the min. number needed to fit something like a 6th order poylnominal for the INL. It is anyway a good question on what polynominal order to use for the assumed soft INL part.

[miro123]

1. Call the ADC transfer function Y(x) = a0 + a1*x + a2*x^2 + a3*x^3 + a4 * x^4 ...
2. For each DAC voltage you measure V(CT,GND) + V(DAC,CT) - V(DAC,GND) to get your error function. For a reasonably accurate ADC, x in the transfer function can just be V(DAC,GND).
3. Run a polynomial fit of the error function to get the coefficients delta(x) = c0 + c2 * x^2 + c3 * x^3 + c4 * x^4  ... (the linear term should be insignificant)
4. Calculate the divider ratio as b = V(CT,GND)/(V(CT,GND) + V(DAC,CT)).
5. The relationships between the coefficients are
     a0 = c0
     a2 = c2/(-2b + 2b^2)
     a3 = c3/(-3b + 3b^2)
     a4 = c4/(-4b + 6b^2 -3b^3 + 2b^4)
     a5 = c5/(-5b + 10b^2 - 10b^3 + 5b^4)

#4. Are you running to chicken en eggs problem?
I did not to the error calculation but my "feeling" is that small error in B calculation introduce huge error in a0....a5 calculation - it is 4-th order polynomial for a5
#4 I also expect that b varies with V(CT) since you are running divider at different power - maybe fake measurements due to thermal EMFs.
Maybe running pythhon script with error estimation /sensitivity calculation/ can help to validate your solution

[Kleinstein]

The sensitivity to changes in the divider ratio is really small, especially of near b= 0.5.  The polynomina in b are only effecting the scaling factors to convert from one decription to the other. So b does not need to be stable / accurate to the ppm level - just the percent level is good enough and it would hardly matter if b changes a little with the voltage (e.g. with thermal EMF or an offest from an extra buffer for the center tap). The need for ppm level (or whatever resolution is needed for the INL) stability and "accuracy" is when getting the error function, as the sum with the 3 or 4 parts. Here it can be starting with up to some 10 V and about getting the values to the 1 µV and ideally better resolution and low noise and repeatablity. With a reasonable good ADC/DVM the sum will be in the µV maybe 10s of µV range.
The relative accuracy for the C0..C5  would not be great to start with and having the fators depending on b to be a little off would not be an issue. It takes a rather poor divider to get changes in b of more than 0.1%.

I am a bit surprized that the conversion from the error function to the INL polynomina is so simple and well behaved. I have not checked the calculation though.  With b = 0.5 the factors are at some 2 , 1.33, 1.33 and 1.066 and thus not very large.  The even powers are anyway likely better measured with a slightly simpler turn over test and one may also inclode a 6th power there.
For the odd power there are than a3 and a5 left, so only 2 parameters to be really meaured with this series of tests.

[miro123]

I agree that C part has less influence in total uncertainty.
I find this idea great but still many thinks are not clear yet.
1. I don't have the full picture of uncertainty even using the idealized models.
2. I think that CT buff cannot be powered from DAC  out.
3. CT buffer CMMR is the smalest issue the problem is that Ib varies with common mode and  Ib also depend from opamp supply voltage
4. But here are many other fundamental questions - what does it mean the error function - Let assume 0,5 divider - ErrorFunct = 2* Error(Udac/2)- Err(Udac) - This function look like regression polynomial, isn't it?
Assuming Udac- 5V that ErrorFunct(5) = U(~2,5)+ U(~2,5) - U(~5)
Later on ErrorFunct(2,5) = U(~1,25)+ U(~1,25) - U(~2,5)
and so on
Another question is what does error function phisicaly represent - error at 5V, at 2.5V or combined?
My point is that It requires calculation the total uncertainty of proposed solution. I see a plenty of error sources - without calculation is hard to say what for accuracy are you gonna achieve.

[Kleinstein]

In the simple form the test does not need a buffer at the center of the divider. The problem here is however that a bias (and common mode leakage) current from the DUT can cause an error that depends on the switch settings to choose which voltage is measured. A buffer at the CT would essentially eliminate this problem as the buffer has not problem driving a current in the nA range. The buffer can add an offset error (directly and via bias and divider impedance), but this error is essentially fixed, at least for the test at one voltage.

There is no problem to power the buffer from the DAC = external tester side, as the CM voltage is well within the supply there. The main point of the buffer is that it is not good to have a variable load there and thus a buffer powered from the DUT side is not good.

The tests with the 3(4) readings that should ideally sum up to zero gives a mix of the INL at  3 points , with the 0.5 divider ratio 2 of them fall together and thus only 2 INL points mixed.
One could see the test as taking the reading at half the reading and than compare the extrapolation to the full value with the reading at the full voltage.
For the test with the full-scale voltage one has a easier interpretation, as the common definition is to have the INL curve at zero for the ends of the range. So INL(FS) = 0 per definiton and one gets  Err(FS)  = 2 x INL(FS/2) for the test. In theory one could than do a 2nd test at Udac = FS/2 and this way get INL(FS/4) = 0.5 * ( ERR(FS/2) - INL(FS/2)) =  0.5 * ERR(FS/2) - 0.25*ERR(FS)

A weak point of the analysis with the polynominal fit is the assumption that the INL is a rather smooth curve and the polynominal approximation is good. It depends on the DUT if this is really the case. For an integrating ADC this may well work, with a SAR type ADC this may not work that well as the INL curve is usally a more stepped function. Even with  an integrating ADC there can also be more lokal error, e.g. from idle tones.

[miro123]

Idea is interesting.
Simulation results are ok. I gonna breadborad one and just for fun I will calibrate one of my ADS1256/PGA280  boards.
Instead of resistive divider I will use MAX5387 because I have some of them in the drawer.

[Kleinstein]

I ran a few tests on the sum of 2 voltages test with my DIY DMM. The switching part is already part of the DMM with 2 inputs and 2 low sides to choose from.  This are effectively 2 double through switches to set the 4 parts of the test. In my case a 0 V reading (to get the offset), some 8.76 V and some 9.24 V from a 9 V block each and finally a 18 V reading as the sum of the 2 voltages.
The readings are 7 readings of 32x1 PLC and than 1 reading that is effected by the switching and droped later for each of the steps. Together a cycle needs some 21 seconds. To allow compensation for the drift 2 cycles are combined and the values are interpolated to a common time.  For a fully automated test one would need the controllable source instead of the 2 x 9 V.

The 2nd attachment shows the more raw data. To get all 4 readings in 1 plot only the last 3 digits and thus a 100 µV wrap around (modulo) is shown.
One can see quite some drift (~ 50 µV for the sum) is present as the batteries are low noise, but not low TC or long term stable. the drift make the interpolation in time mecessary.
The 1nd graph shows the calculated residual for the  summation (0+18-9-9): there are quite a few outliers, but many of the points are around 7.7 µV.
Some of the outliers are likely from popcorn noise in the DMM reference (LM399). Similar errors from the external votlages are also possible.

To get a reasonable stable result it needs quite a bit of averaging / not as much as used here, but some 20 repeats for the cycle seem to be a good idea. So this would be some 15 minutes for 1 point to the curve. Of cause the time needed depends on the ADC / DMM to test. For a reasonable polynominal fit it would need maybe 10 points at least, better quite a few more.

[Kleinstein]

I analyzed a few more of the data, as an example on how such a curve may look like. The voltages are set by sets of alkaline batteries (some older and thus not all 1.5 V).
The curve shows the residual of the sum test for a few test points in the 20 V range (the prime range of the meter). The actual ADC sees +U/2 and -U/2 and thus kind of does an internal turn over.  So the turn over error is very small and the 2 points measures with a negative voltage are also just symmetric.  So the error curve should mainly have the odd powers.

The fit  with 3 odd powers  is a bit of a stretch with the limited number of points. Only linear and 3rd power however does not give a good fit.
The blue curve would be the err polynominal converted to INL error (with the linear slope adjusted to about overall low error). Due to the limited number or points this is more for demonstration, not a serious result.

The data so far are a bit crude, but with an easier way to change the voltage and thus more points with less user interaction the test method looks promissing.
Even the batteries as test voltage look OK, though not great and much of the drift can be corrected. The demand main on the reference for this test is low noise. Low drift is not really needed, though it could help a little. Other tests, like the originally planed sum of many similar steps would be more sensitive to drift (at least more difficult to correct). So low drift can still be desirable.

[guenthert]

If I'm not mistaken, one difficulty lies in distinguishing actual non-linearities from offsets due to thermal EMF.  I'd think the method using a resistor string has the advantage there as it allows to reverse polarity of the driving voltage w/o detaching/re-attaching a probe.

[Kleinstein]

If done with moving around cables the thermal EMF would indeed be a big problem. The test should use something like relays or CMOS switches to switch between the 3 or 4 voltages to measure. This are 2 single pole, double through switches: one each for the high side and low side for the DMM / DUT.  The nice point with the test (4 voltages including the zero) is that in the sum each of the switch contacts enters twice with a positive and twice with a negative sign. So any fixed offset or thermal EMF at any of the swich connectors will cancel out.  For the automated test the thermal EMF is thus no longer an issue.

A polarity reversal could than be done manual (change the connections) for a separate run. So it could be enough if the test source is one polarity. It does not matter if the offsets / thermal EMF would change between the runs. Also a slow drift during repeated test sets are not am issue. A nice point with the sum test is that only 4 readings are critical as a set and long term drift is not that critical.


One weak point with the test is reference noise, that can make the test a bit noisy and thus slow. At least the LM399 in my case is a real issue and due to the jumps they produce quite some outliers and thus makes the test slow. So one shoud have a really low noise reference (e.g. LTZ, ADR1399 ?, LTC6655) at both the external source and DMM. With only 4 voltage readings for a sum one can at least limit the effect of very low frequency noise - the test with the resistor string would be even more sensitive to ref. noise due to a longer time for a set of readings.

Another weak point is the assumption of a smooth INL curve. So a more local / jagged INL contribution (hard INL) can interfere with the calculation back the the INL curve. One can still get the residual error from the sums as spot tests for the linearity, but it would be hard to really calculate back to the INL curve. It would at least need quite some test voltages to hopefully average out more local effects. For the more loacl INL errors one would need a separate test.

The sum of equal steps from the resistor string definitely has an advantage that the interpretation of the result is easier. One kind of gets a limited set of points for the INL curve. One however still has the assumption that the INL error for the step size measurements (e.g. 5-10% of FS) is about equal. The number of points in the curve is limited as with very small and thus more  steps more errors add up and noise / drift gets more of an issue. Because of the drift one would likely want automated switching of the connections and thus quite some relays / CMOS switches.
The problem with the hard INL is similar, just only for a more limited range around the step size. With the limited number of points / steps in the string the averaging it out is bit more tricky.
Ideally one would do both tests - they test different aspects of the INL and at the very low levels and extra check is a good thing.

[iMo]

What if I would have got, for example, two 0..12V output 12bit DACs, both fed by the same Vref, and the DUT/meter will be wired between the DAC's outputs floating. Will that help somehow?

[Kleinstein]

The 2 DACs would allow getting positive and negative voltages. One could also average out errors of the DAC be using different combinations for nominally the same result, at least with many values in the middle. Still the avearge of 2 12 bit DACs would not be that good to be really helpfull as a highly linear source.

There is a way to use the 2 DAC also as a stack of voltages, but as far as I see with an extra complication of 2 types of step (e.g. a positive and negative). At least I don't see a good way to use it to replace the string type test.


For just the simple sum of 2 equal voltages test it would only need 1 DAC. 12 Bit could be good enough, if the DAC is low noise (e.g. many current output types). Depending on the meter to test one may want additional scaling (e.g. for a 20 / 10 / 2 / 1 V range), than a divider with just 2 about equal resistors (nothing special needed just cheap thin film to avoid extra noise). I would prefer a buffer amplifier for the divider center, especially if the DMM to test is not super low bias. The buffer should not be tricky for high voltages like a 10 V or 1 V range , maybe with 100 mV and less.
The main part for the test are the 2 switches for the DMM inputs - if not at the DMM this could be DMOS switches like DG419 / DG413 with the reference. I would consider a DIP version in a socket and than skip on extra protection.
For the links from the voltages  to the switches one may want some jumper options to allow also the turn over version.

[CurtisSeizert]

Another question is what does error function phisicaly represent - error at 5V, at 2.5V or combined?
My point is that It requires calculation the total uncertainty of proposed solution. I see a plenty of error sources - without calculation is hard to say what for accuracy are you gonna achieve.

I haven't tried to analytically determine the uncertainties in this, but I did write some code in python to see how it does when there is noise. I don't consider Ib dependence on Vin to be something that is necessary to confront here since that can be measured separately. The equations I presented are to determine the transfer coefficients at V(DAC,GND). The code is kind of a mess, but here it is:

Code: [Select]


import numpy as np
import numpy.polynomial.polynomial as nppoly
import matplotlib.pyplot as plt

def displayplot(title=None):
    plt.figure(dpi=600)
    plt.plot(Vin, uV_errors, label='Noiseless')
    plt.plot(Vin, uV_errors_n, label='With noise')
    plt.plot(Vin, uV_errorscalc, label='Calculated')
    plt.plot(Vin, uV_errorscorr, label='Corrected')
    plt.legend()
    plt.xlabel('Voltage')
    plt.ylabel('Error (uV)')
    plt.grid(visible=True, which="both", axis="both")
    plt.title(title)
    plt.show()

rng = np.random.default_rng()

#parameters
numpts = 101
Vmax = 10
Vmin = -10
divratio = 0.5
sumfitorder = 5
revfitorder = 4

'''transfer function coefficient array as
deviations from linearity in ppm
y = A + Bx + Cx^2 + Dx^3 + Ex^4 + Fx^5
B represents gain error and cannot be calculated.
The index of the array is the order of the term.'''

tcoeff = [-0.6, 0, 0.0035, -0.0013, 0.0000097, 0.000006]
calcdcoef = np.zeros(6)
torder = 5
stdev0 = 0.03 #zero order noise, uV
stdev1 = 0.05 #first order noise, uV


#calculated parameters
Vint = (Vmax - Vmin)/(numpts - 1)

Vin = []


'''Calculate input voltages'''
for x in range(0,numpts):
    Vin.append(Vmin + x * Vint)
   

'''Calculate low divider voltages'''
Vin_divl = []

#calculate input voltages
for x in range(0,numpts):
    Vin_divl.append((Vmin + x * Vint)*divratio)
   

'''Calculate high divider voltages'''

Vin_divh = []

#calculate input voltages
for x in range(0,numpts):
    Vin_divh.append((Vmin + x * Vint)*(1 - divratio))
       

   
'''Calculate error voltages'''

uV_errors = np.zeros(numpts)


for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errors[i] = uV_errors[i] + tcoeff[x] * Vin[i]**x - calcdcoef[x] * Vin_divl[i]**x
       
'''Add noise'''

uV_errors_n = np.zeros(numpts)
uV_errors_nr = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_n[i] = uV_errors[i] + stdev0 * rng.standard_normal() + Vin[i] * stdev1 * rng.standard_normal()

for i in range(0, numpts):
    uV_errors_nr[i] = uV_errors[numpts-i-1] + stdev0 * rng.standard_normal() + Vin[numpts-i-1] * stdev1 * rng.standard_normal()
       
       


'''Calculate reversal error voltages'''
uV_errors_rev = np.zeros(numpts)
for i in range(0, numpts):
    uV_errors_rev[i] = (uV_errors_n[i] + uV_errors_nr[i])/2
   
#offsetrev = np.average(uV_errors_rev)
#uV_errors_rev = uV_errors_rev - offsetrev


revfitorders = [0,1,2,4]


revpoly = nppoly.polyfit(Vin, uV_errors_rev, revfitorders)
fit_coeffs = nppoly.polyfit(Vin, uV_errors, sumfitorder)



calcdcoef[0] = revpoly[0]
calcdcoef[1] = 0
calcdcoef[2] = revpoly[2]
calcdcoef[4] = revpoly[4]


   

'''Calculate low divider error voltages'''

uV_errors_divl = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_divl[i] = uV_errors_divl[i] + stdev0 * rng.standard_normal() + Vin_divl[i] * stdev1 * rng.standard_normal()
    for x in range(0,torder + 1):
        uV_errors_divl[i] = uV_errors_divl[i] + tcoeff[x] * Vin_divl[i]**x - calcdcoef[x] * Vin_divl[i]**x
       
       
'''Calculate high divider error voltages'''

uV_errors_divh = np.zeros(numpts)

for i in range(0, numpts):
    uV_errors_divl[i] = uV_errors_divh[i] + stdev0 * rng.standard_normal() + Vin_divh[i] * stdev1 * rng.standard_normal()
    for x in range(0,torder + 1):
        uV_errors_divh[i] = uV_errors_divh[i] + tcoeff[x] * Vin_divh[i]**x - calcdcoef[x] * Vin_divl[i]**x
       

'''Correct total voltages'''
for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errors_n[i] = uV_errors_n[i] - calcdcoef[x] * Vin_divl[i]**x

'''Calculate sum error voltages'''
uV_errors_sum = uV_errors_n - uV_errors_divl - uV_errors_divh
offsetsum = np.average(uV_errors_sum)
uV_errors_sum = uV_errors_sum - offsetsum


sumfitorders = [0,1,2,3,4,5]
sumpoly = nppoly.polyfit(Vin, uV_errors_sum, sumfitorders)
tsumcoef = np.zeros(sumfitorder+1)
tsumcoef[2] = sumpoly[2]/(2*divratio - 2*(divratio**2))
tsumcoef[3] = sumpoly[3]/(3*divratio - 3*(divratio**2) + divratio**3)
tsumcoef[5] = sumpoly[5]/(5*divratio - 10*divratio**2 + 10*divratio**3 - 5*divratio**4)

calcdcoef[3] = tsumcoef[3]
calcdcoef[5] = tsumcoef[5]

'''calculated transfer errors'''

uV_errorscalc = np.zeros(numpts)

for i in range(0, numpts):
    for x in range(0,torder + 1):
        uV_errorscalc[i] = uV_errorscalc[i] + calcdcoef[x] * Vin[i]**x
       
uV_errorscorr = uV_errors - uV_errorscalc


displayplot()
print("Coefficients: ", tcoeff)
print("Calculated coefficients: ", calcdcoef)

The code uses reversal to determine the offset and second order coefficient then uses that to apply a correction factor for those terms before doing the regression for the sum error. This seems to work a bit better than doing everything separately as there are fewer degrees of freedom for reversal, which only has even order coefficients. As expected, the more points you get, the better the immunity to noise. I have attached a couple plots from running the script with some random coefficients I had chosen, one where it does well, and one where it does poorly. Noise is modeled as conversion noise that is constant at all input voltages and reference noise that scales with the input voltage.

I have nearly finished up the board I am currently working on, so I will design something along these lines in the coming weeks.

[Kleinstein]

The polynominal fit can get a bit tricky and increasingly sensitive to noise, when higher orders, like 7th or 9 th order are inlcuded.  If the actual INL is not well described with a low order polynominal one might have to include those higher terms, at least from the theoretical side. Ignoring them would not improve the result, but make it worse.
So if the INL is not well descibed by low order polynominal the calculation back may become tricky. The factors to go from the cn to an coefficients for a 1:1 divider should be - 1 - 1/(2^(n-1)-1) for n > 1 and thus convert to 1 relatively fast. With possibly opposing signs and relatively large values this could still be an issue for the higher powers.

Test with the sum from the half way point still makes sense to check, it may just be hard to calculate back to an INL curve if the curve is not well behaved.


For the hardware side I did a few more tests. One point that may be interesting is that the impedance of the divider can make a difference. This is especially if the DUT or possibly the switching part is not super low bias / leakage. In my case a series resistor of 6.8 K for the center voltage changes the sum of the 4 readings by some 1.5 µV.  An extra buffer for the divider voltage would essentially eliminate the effect. Without a buffer a test with an extra series resistor may be a good idea to check for the approximate effect of output impedance.

[miro123]

I am still struggling with HW implementation. I did simple mistake.
I have MAX5216 available, but I overlooked the datasheet noise section.
DAC output is really very noisy and useless.  Reducing the BW does not help a lot.
Actually the datsheet has already described. It is my fault.
Vn= 73nV/sqrt(Hz) @ 1KHz
Vn= 70nV/sqrt(Hz) @ 10KHz
Vn(0,1..10Hz) 3,5uVpp

I have looked for low noise DAC but their price is quite high for such simple hobby project.
Doe somebody knows - low noise DAC, available on stock and with reasonable price?  Or do I  ask a lot? :-)

[Kleinstein]

I have also looked at low noise DACs. A good choice are the current output DACs and there are many similar types to choose from. An example is AD5443 (12 bit) and AD5446 (14 bit).
The noise should mainly be set by the resistance and OP-amp for the output (e.g. OPA207) - the slight unknown is if the resistor part has significant excess noise. The example noise performance in the DS uses a rather fast OP-amp with lots of 1/f noise and the LF part is thus dominated by the OP-amp.

[julian1]

I tried in the past with dac8734 (1uV RMS 0.1-10Hz) but it was a bit noisy.

For AD5444/5446 -
ref input can be +-10V. which means using a ~7V ref is OK.
the multiplying r2r dac outputs are limited, to VDD, max +7V.
But R2 working as an extra resistor in front of the internal Rfb,  can add gain for both the unipolar and bipolar reference circuits,
So this would work for eg. +-10V output.

What would be a good configuration for sum tests?
One could have one multiplying dac with bipolar output to create the first voltage.
And also use the output as input ref for a second multiplying dac to create a controllable buffered divider.

Alternatively, just one multiplying in a bipolar configuration - followed by a fixed divider (eg. 10k,10k) to create a second midpoint voltage would be enough.

[Kleinstein]

The basic configuration for the multiplying DACs is with some 10 or 7 V reference and than 0 to -10 or 0 to -7 V out. So an output gain of  0 to -1.
The supply to the chip is for the switches and the ref. voltage can be higher and even negative. It is a bit tricky to directly add gain, as Rfb is matched to the resistors in the R2R DAC part. So gain would be relatively separate from the DAC. The bipolar version is a bit tricky with extra precision resistors needed.
One may not even need a negative sign. For the negative half one could just change the wiring from the meter to the tester. This would mean running the test as 2 parts.
An extra inverter for an alternative signal with the other side also makes some sense (see below).

A main case for the sum test is having 1 voltage and half the voltage. It would be relatively few divider ratios that really make much sense. So I see little sense in a 2nd DAC for this.
A 2nd DAC may be usefull for other tests, maybe getting close to the chain of voltages as in the original idea: One DAC sets the even voltages and the other the odd ones. For the overall test one would also have ground as a 3rd path for the switches to the DUT terminals.
With buffered signals, leakage would be not critical als relatively simple CMOS switches (e.g. DG411) would likely be good enough for switching.
The general setup could be 2 MUX chips like DG408/9 and a bunch of test signals to choose for both sides. The question may be if one wants protection (one side can be enough) towards the DUT(meter) or take the risk of possibly damaging the switches(e.g. from ESD or a short).

If the 10 V range is enough one could use just the DAC output and a divider. It could make sense to have a buffer for the resistive divider to avoid a loading effect. I would consider a small offset the lesser problem than the output impedance of the divider.

For a larger (e.g. 20 V) range one could consider driving both sides and use an extra inverter after the DAC to kind of replace a 1:1 divider by some effective gain of 2 for the signal between the positive and negative output and ground as the center point. Compared to normal gain this would not need a higher supply and may be more convenient with CMOS switches to have the same GND as the DAC.
This way one would also have the other sign available for other tests.

So possible test signals to the mux chips could be:
1) the DAC output  (e.g. 0 ... -10 V)
2) inverted DAC out   0 ... 10 V
3) GND
4) 1:1 divider from DAC    + buffer  (e.g. 0... -5 V)
5) optional:  1:1 divider from - DAC  + buffer  (e.g. 0... 5 V)
6) possibly a 2nd DAC
7) possibly the raw 7 V or 10 V ref.
?

[julian1]

Is there any way to guess at the possibility of excess resistor noise - for different part choices?

Rfb is a proxy for the values of all other switchable resistors.
The size of Rfb varies, but lower values (5k versus 7-12k) may risk more thermal effects.

Judging by max VDD they all use typical cmos process nodes
It appears there are many ways to do resistors,
https://aicdesign.org/wp-content/uploads/2018/08/lecture07-140310.pdf

But I think only metal thin-film has good enough TC, to meet part datasheet specs, so perhaps thin-film could be assumed?
Maybe tests are the only way to know for sure.

As Kleinstein notes, the datasheet 1kHz noise figures are likely meaningless for LF DC, but relate more to the fast op-amps used for test setup circuits.

The AD part, is nice in that it brings out a separate gnd for the resistors.

AD5444_5446
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
Fig. 39 shows output noise ramping at lot <1kHz / AD8038.
Rfb 7-11k.
DS states resistors are thin film - "consideration the effect of the temperature coefficients of the thin film resistors".

RM10 mssop 10.   0.5mm pitch.

LTC1595
Equivalent DAC Thermal Noise Voltage Density (Note 10) f = 1kHz 11 nV/√Hz
Rfb 5-10k,  7k typ.
soic-8.   1.27mm   4mm width.

DAC8811.
Output spot noise voltage f = 1 kHz, BW = 1 Hz 12 nV/√Hz
doesn't say Rfb, but probably the same as dual DAC8812, which gives Rfb= 5k.
dgk = vssop.  0.65mm.

DAC7821  12bit dual
Rfb  8 to 12k.
tssop-20.

[julian1]

Sorry for the edits.   

Got a nice statement here from AD, that white/thermal noise is dominant,

"Low noise — the AD54xx and AD55xx family of IOUT DACs utilize low impedance architectures. These are inherently low noise architectures dominated by the thermal noise of the RDAC resistor."

https://www.analog.com/media/en/news-marketing-collateral/solutions-bulletins-brochures/AnalogMultiplyingDACs.pdf

And the resistors are silicon/chromium thin-film,

"The AD5449 (and the AD5415) are dual CMOS multiplying DACs (MDACs). They are
made with silicon/chromium thin film resistors and CMOS switches. Since the
resistance of the CMOS switches is much lower than that of the resistors in the
network the noise of such devices is quite close to the thermal noise of the
resistance. "

https://ez.analog.com/data_converters/precision_dacs/w/documents/3490/ad5449-output-noise-spectral-density

[Kleinstein]

The white noise part from the normal resistor noise should not be that important. The LTZ1000 has a white noise part that about corresponds to a 100-150 K resistor. The point to possibly worry about is the low frequency noise. For the multiplying DACs this is mainly excess noise from the resistors and maybe a little from the FETs.
Because of the thermal effects I would prefer the slightly higher resistance variants, especilly if a 10 V or even slightly higher reference is used. I would consider the rather low resistance version more suitable for lower ref. voltages (e.g. 5 V).

It is hard to tell how much excess noise the ADCs have. The resistor arrays on a silicon substrate usually have low excess noise, but this is usually NiCr and not CrSi.
I see a good chance that the DAC noise would be lower than the noise of the reference also for the LF noise.
The noise data I have found so far all included the noise from the OP-amp at the output and possibly the ref. drivers.

Having separate analog and digital ground may be an issue for higher speed operation. I don't see an issue with relatively slow changing values. With only 1 GND pin (e.g. DAC8801) it should go to the analog ground as it is the return path for the DAC current. So any ground bounce here would add to the output. A seprate digital ground is nice (e.g. helps with decoupling), mainly a thing if one uses the DAC with fast changing data. With only 1 GND pin I would definitely include a series resistor / ferrite in the supply path to reduce coupling from the digial supply to the analog ground.

[CurtisSeizert]

Kleinstein,

I think the best way of dealing with the impedance issue is not to buffer the divider output but to put resistors equal to the impedance of the divider center tap at all the outputs. With regards to the higher order INL terms, they may be an issue, but most of the differential ADCs I see have third order errors being the biggest issue. This method is probably better suited for higher order terms than a string DAC. Most polynomial regression algorithms treat x, x^2, x^3... as independent variables in a multiple regression, so one quickly runs into the problem of overfitting the data set and fitting noise. I would need to review the guidelines for minimizing this problem, but larger data sets with replicates are going to help. With a 16-bit DAC, time is always going to be the limiting factor in how many points one wants to do. Algorithmically, you could imagine running a reasonable number of points (say 100), running the regression through fifth order, and re-running points with a large residual. If the residual goes down by a certain amount when you average the old data point and the new one, you can say it is noise, but if it does not, it may be that you have not captured terms to a high enough order.

I have finally finished laying out my NVM, so I will begin working on a design for this shortly, but my general philosophy is for things I am going to make one or two of, I'll spend $100 on a DAC without hesitation because I will inevitably be putting in many hours of labor as well as ordering boards, stencils, enclosures, etc. My plan was to use a DAC11001B and use an INL test of my 3458a to measure the nonlinearity of the source to be able to use it as a calibrator. The power supply will be 4S lithium cells with a LT1533 push-pull converter to generate +/- 15V as well as some other taps.  By the way, you can order DAC81001s (a 16-bit version of the 11001) directly from TI. They are about $30 in unit quantities and have the same footprint as the 18 and 20 bit versions. The noise on these is low enough that reference voltage noise is likely to be dominant.

[Kleinstein]

I like the idea if re-running those points with a large residual. When doing things manually one tends to do this also, making sure the points are real and not due to some odd effects.  This may however also be tricky as if one is not careful adds more weight to regions that show the larger initial residual.

For my setup, that is ADC noise wise comparable (to slightly better) to the 3458, but so far has only a LM399 ref. it takes quite some time for a set of voltages / point in the crive. Uusually some 10-20 minutes. It may get a little better with a better reference, as part of the averaging is needed for ref. popcorn noise that just need some averages. Even with a lower noise reference I don't see it getting much faster than some 5 minutes ( ~ 15 readings for each setting). So this would be some 200 points at most for 1 day of running the setup.  100 points sounds like a reasonable number, with possibly separate sets to check for reproduciblity and drift effects.  At least for this test there is no real need a really high resolution of highly linear DAC - 12 bits would be plenty. Of cause a different test may make good use of a better DAC.

For my ADC I was also expecting mainly an X³ term - but the data points I got so far did not support this. There seems to be more.
The even powers are usually easy to handle with the turn over test and in my case that part works really well.  So the main fit would be with only the odd powers and even with x, x^3,x^5 and x^7 there are not that many parameters to fit. A problem in the fit is that the X^5 and X^7 powers and similar higher orders still look relatively similar for most of the points. So only a small part of the data near the full scale will really make a difference. The points near zero have little effect on this more critical part of the fit.
One should still be OK to fit something like 5 or 6 parameters with suitable spaced testpoints, like more points near the ends.

Adding resistance to make all test points the same impedance may not be enough, as 2 links (input and low side) to the DMM and swiches may not have the same amount of leakage. This would especially be the case if the switches are powered from the ref./DAC unit. Also more impedance make the whole setup more sensitive to hum.
I see no problem with adding an extra buffer to the dividers - this is at least for the more high voltages like the 10 V range. The sum error does not change much when a little off the 50:50 point and the offset would be only a tiny fraction of the test voltages.
Things can be different for very low voltages, e.g. for a 100 mV range and below. There the divider can be much smaller resistance too.
Having provisions to add resistors may still be a good idea - similar it is good to have the option of an extra buffer.

[CurtisSeizert]

Interesting observations about your own test, and good point about optimizing the spacing.

Regarding the input buffers, my thought was that most low noise buffers will not do as well as an autozeroing input stage in terms of maintaining high impedance as well as low offset, but if the design to be tested did not have a high input impedance, then this could be problematic. For the design I am planning out, I plan on using something like a 19:1 divider to scale the input voltages down to 0-0.5 V, then buffering that and dividing with a three resistor string of something like 450R, 25R, and 25R. The "V_dac" would be taken from the tap between the 450 and top 25R resistors, and the center tap would be taken from between the two 25R resistors. An additional 22R at the center tap to the output would put both impedances at ~45R. I agree that at 100 mV and below, a buffer is probably not practical. In general, the choice requires one to make some assumptions about the input impedance and noise of the DUT.

I wonder if thermal tailing would be an issue if the divider for the main 10V output was, say 1k/1k. My instinct is probably not as the whole test is quite slow and the steps are fairly small, so the increase in power dissipation would not be very large. One could drive such a divider with a 3904/3906 pair without concern for biasing as you would not be crossing 0V quickly. This would keep the loop gain of the buffer amp high and isolate it from thermal EMFs.

My main motivation for using a 20-bit DAC is because measuring the INL of an ADC simultaneously allows one to measure the INL of the source, so the whole thing can serve as a voltage calibrator once the DAC's transfer function is characterized.

The MAX549x resistor networks use SiCr thin film, and these have a measured noise index of -55 dB (https://arxiv.org/pdf/2109.02448.pdf). Of the thin film types, NiCr seem to generally be the best.

[Kleinstein]

For the higher voltage the buffer would not be an issue at all. Even if not super low offset of input bias the buffer only sees the fixed divider and thus a fairly constant impedance. So any bias would only add a little offset. A little offset is not that critical: the offset does not directly add to the error sum, but effectively changes the divider to a slightly different value. The actual ratio is measured in the test and thus could be used. I see no problem if the divider ration is a little off - this only slighty increases the dependence on the ratio. If we have some 100 µV of offset and a target of 1% deviation for the divider this would still be only 10 mV for the partial voltage and 20 mV total.

Having 10 V with 1K /1K would likely run into thermal problems: that would be 5 mA and 50 mW. With such low resistors one might get away without a buffer for the center tap.
For the divider I would  more consider 10K/10K and even than there can be some thermal effect, though not sure if this would be an issue for the test.

[CurtisSeizert]

I finally got around to putting together a schematic for the single divider version. I also need a general purpose calibrator that is reasonably accurate, so that guided some of the design decisions here. The low voltage range will be good for testing INL for ranges up to 100 mV. A pdf of the interesting part is attached. The power source will be a 4S 21700 Li battery with isolated and coupled-inductor Cuk converters for the primary positive and negative rails, respectively.

[Kleinstein]

The circuit at the output of the DAC11001 looks a bit odd. As shown it is a glorified buffer amplifier with the 2 DAC internal resistors just in sereies at the feedback.

[EC8010]

I see that a great deal of thought has gone into data analysis and circuit design, but nobody has mentioned the issue of ensuring that everything is at the same temperature. For a similar problem, I fitted my parts in a sealed can, collected noise spectrum down to 20mHz, then added oil and repeated. Measured improvement as attached. Those frequencies look to be in the time scale this thread is considering. I would warn that white oil leaks through tightened threads, solved by using silicone sealant as used for assembling engines.

[CurtisSeizert]

The circuit at the output of the DAC11001 looks a bit odd. As shown it is a glorified buffer amplifier with the 2 DAC internal resistors just in sereies at the feedback.

This is the recommended configuration from the datasheet for unity gain output with matched source impedances for the buffer. The two internal resistors are in parallel as shown. The circuit is indeed just a glorified buffer, but you can have good buffers and bad ones, and I think this is a reasonable occasion for a good one.

I see that a great deal of thought has gone into data analysis and circuit design, but nobody has mentioned the issue of ensuring that everything is at the same temperature. For a similar problem, I fitted my parts in a sealed can, collected noise spectrum down to 20mHz, then added oil and repeated. Measured improvement as attached. Those frequencies look to be in the time scale this thread is considering. I would warn that white oil leaks through tightened threads, solved by using silicone sealant as used for assembling engines.

You are more dedicated than I am. Oil is a mess. I like to use the cheap Laird SMD RF shields as baffles to minimize airflow, and this works pretty well for reducing LF noise coming from thermal EMFs. My general plan here was to put the output switches reasonably far away from the other components, possibly with isolation slots. I think the TSSOP will be better than the QFN in this case because it will be possible to orient the terminals for each switch perpendicular to any thermal gradients. The lower voltage rails for the LT6018, the fact that I am using an LTZ1000A with a cathode resistor to get good TC with a lower heater setpoint, and the design of the power tree are all ultimately in service of the goal of minimizing power dissipation to make it easier to avoid excessive noise from thermal gradients. Those last two aren't shown here, but this has certainly been a design consideration.

[miro123]

I finally got around to putting together a schematic for the single divider version. I also need a general purpose calibrator that is reasonably accurate, so that guided some of the design decisions here. The low voltage range will be good for testing INL for ranges up to 100 mV. A pdf of the interesting part is attached. The power source will be a 4S 21700 Li battery with isolated and coupled-inductor Cuk converters for the primary positive and negative rails, respectively.

What is the internal DAC1101 structure?  In case of MOS SC the reference circuit should provide sink as well as source capability. The datasheet reference circuit uses sink&source buffer - no idea is this intentionally.
Sems to be SC,
1. It is logical there is no way to make such high performance device with resistors
2. datasheet shows  - THS4011 as Vref buffers- 290MHz 310V/us
3. datasheet page page 24 - "The reference pins are unbuffered; therefore, use a reference driver circuit for these pin"

[Kleinstein]

The datasheet says R2R type for the DAC. The lack of a clock (except for SPI) also sugest that this is not a SC DAC.

[CurtisSeizert]

The REF+ buffer only needs to source current and vice versa for REF-. On p. 18 of the datasheet there's a graph of the current draw from each reference pin. Thinking about this now, it might be a good move to put a resistive load between the two to increase the transconductance of the emitter followers when the load from the DAC is light. The current profile for the reference pins drops to nearly zero at the extreme codes, which seems indicative of it being an R-2R ladder rather than a string DAC for the MSBs and an R-2R ladder for the LSBs like the AD5791. The B version also implements a sample and hold deglitching filter, so in fairness, there's at least one switched cap in there.

[CurtisSeizert]

I finished layout and assembled a board for the DAC + single ratio version. I wanted to get my money's worth for the LTZ1000A and DAC11001B I used, so I added a Howland-type current source with four ranges and a fourth order Butterworth for an AWG on separate outputs. Those are on switched rails to minimize power consumption and heat dissipation. I am hoping to get the firmware to a point where I can test it with my 3458 in a week or so, but I expect I'll need to run it for a month or so to get the LTZ1000 stable enough for optimal results.

[Kleinstein]

For just INL test it should not take so lang for the LTZ1000 to stabilize. The more tricky part can be drift at other parts (OP-amps, resistors and the DAC)  from board stress and humidity changes. Ideally the INL test sequence would allow for some constant drift at least. The drift can be from the ref. source, but also the DUT.  As an example have a sequence like full voltage, upper half, lower half, maybe the upper half again and than full voltage again. One may want to repeat the tests multiple times anyway, especially if there can be popcorn type noise as this can cause outlyers.

[CurtisSeizert]

Fair enough. I baked the board at 125 C for 60 minutes after reflow (but before populating the TH components) per the DAC11001B datasheet, but in my experience, it takes some days of on time for things to settle out.

It will be important to characterize the settling behavior of the source and DUT to determine the best way to order the data points while keeping the overall run time reasonable. If there is a non-linear component to settling or drift, that will not be cancelled effectively with an ABCCBA sequence. Also, ideally the sequence of DAC codes would be random (if there were no parasitic effects for the source to consider) because running everything in order would make time dependent gain drift of the DUT appear as INL. However, there will be some inevitable thermal tailing due to power dissipation in the 10k/10k divider that will increase the settling time for large code steps. As such, it will probably be necessary to check for settling or group codes into blocks that would be randomized in both placement and direction if settling time is excessive. Also, to the extent that a power dependent error term exists in the DUT, incomplete settling for the readings taken at a given code will lead to second and/or third order INL terms. The weight of these error terms will depend on whether the DUT input range is bipolar and to what extent the effect is on offset through e.g. parasitic thermocouples or gain through resistor ratio drift.

With those considerations in mind, it would be hubris to predict which run order would be best a priori without system feedback. So, to start off, I will run some tests to compare the results of different ways of structuring the run with my 3458. My gut feeling is the best algorithm will capture a number of data points for each code + switch position at, say, 10 NPLC and take a standard deviation of the x most recent of these. Once the standard deviation stops dropping, take the average of those x most recent and record that average and move to the next point. Some degree of randomization will almost certainly be necessary as will replicates for either the entire run or for outliers. I think that it will be wise to collect temperature data for both the DUT and the source at each point as well to be able to run a diagnostic fit of residuals against temperature (as well as the usual fit against order and checking for normality).

For the polynomial fit of the sum and reversal errors, my plan is to work these up as one would a data set for multiple regression or design of experiments. Before the run, the number of points would need to be chosen to be sufficiently large to avoid over fitting the data based on the highest order INL term I plan to fit. Once I have the data, I'll run multiple regression and prune the least significant terms from the model until this starts to increase the standard error or adjusted r^2. I will probably use reversal error for the even-order terms and sum error for odd-order to limit the degrees of freedom on the sum error fit. Best practice (at least in process chemistry, which is where I would do this stuff and get paid for it) would be to run replicates for points above a certain threshold standard deviation from the model then generate a sample of random data points not included in the initial run to check their fit to the model to validate its predictive power. None of these can necessarily pick up systematic errors, which is why it will be important to handle that aspect separately through robust experimental design.

I will post the data I get once everything is up and running.

[CurtisSeizert]

I've got the core functionality of the design up and running, and everything seems reasonable at this point. The current draw at 16V is 140 mA, so battery life with 21700 cells should be 24h with margin. I am waiting on a trim resistor to get the +10V reference voltage to 10.48576 V to give a 10 uV LSB for the 10V range. The low voltage part is very quiet and has a range of +/- 100 mV (or less, depending on the reference SW position), so I should be able to also get INL tests for the low range of the 3458 and my NVM in the future.

I've included the results from the only real test I have run so far, including the raw data if anyone wants to play around with it. The DUT is my 3458A. I used 50 DAC codes evenly spaced in a random order. For each code, I measured voltage at each of the eight possible switch settings (DAC,GND; CT,GND; DAC,CT; CT,CT + the reverse). For each setting, I took 20 samples at 100 NPLC, kept the last 16, and recorded the average and standard deviation of those 16. I ran ACAL right before the run, but it's been a while since I did a short calibration, so null is a bit off. The total run time was about 7 hours.

For future tests, I will see if it is actually important to randomize the order of the codes. I suspect it is not because gain drift between codes would be second order effects that would get lost in the noise with any reasonably accurate DUT. I am also going to try random SW position order but maintaining the CT,CT settings as bookends. I do think this will be more consequential.

Standard deviations were reasonably good, averaging about 40 ppb of full scale at the ends and 11 ppb of full scale in the middle. With 16 samples, the total width of the 95% confidence interval is equal to the standard deviation, so getting sufficiently low scatter for moderate order polynomial fits at sub-ppm level should be feasible in 24 hours or less. There reversal errors at the center tap voltages that are in excess of those measured between DAC and GND by several-fold (average is 3-4 uV). I don't know why these should exist other than that they may come from parasitic thermocouples between the leads of the switch. I will try compensating those for future runs by switching the DAC to bipolar references, running codes on either side of zero sequentially, and averaging the error terms for each. I think this will help to avoid confounding non-idealities in the source with DUT nonlinearity.

Anyways, with the sum errors (corrected for offset at CT,CT), there are a couple points that I would probably discard or rerun for a fit, but there is a clear shape to the curve. I subtracted out reversal errors for each voltage in the sum to get "corrected" sum errors. This makes the plot symmetric about the origin, but it's not far off from that uncorrected (less the offset, of course). This correction should cancel out the even-order errors in both source and DUT, which is fine because we can determine the even order terms in the transfer function from the reversal error fit. Just by looking at the corrected sum error plot, it seems the dominant term is fifth order with nonlinearity errors topping out around 50 ppb. It will be interesting to see if this shape remains with the bipolar compensation scheme I mentioned. The magnitude of the reversal errors is smaller, and without doing the analysis, my gut feeling is that the experimental power is probably not sufficient to put any even order error terms in an INL model. Overall, I am optimistic that this source could be used to characterize INL down to at least the 0.1 ppm level if the transfer function is well-described by a polynomial fit without too many terms.

I also modeled the DAC linearity error, but this isn't really a good way of measuring it because of the amount of time spent measuring other things and the greater opportunity for drift. Here I saw maximum deviations from linearity of about 22 uV, so 2.2 ppm. I did a quicker run before this, and it was within the DAC11001B's +/- 1 ppm spec.

[Kleinstein]

For the DAC error the drift of the reference / gain at both the DAC and meter can definitely be an issue. This may especially effect the first point, when the system is possibly not yet fully settled. It still does not look that bad, expect for a few outlyers.

For the sum tests the drift is far less critical. It is mainly about the drift during the 8 readings.  One may also just run the test with only 4 readings that belong together and maybe than repeat that same 4 values 2 or 3 times. The other polarity is more like a different test. The combination gets 3 tests from 8 readings instead of 1 test from 4 readings. So it could save some time.

Some of the turn error can come from an offset at the meter, e.g. from termal EMF at the terminals / relays use for the reversal. One gets 2 x the meters offset as turn over error.
One may get around some of this if the turn over test includes a zero reading from the same switches as used for the source reversal.
How is the reversal done exactly ?  Is it just the sum of 2 readings or is it 4 readings inlcuding 2 zeros ? Including the zero readings would compensate for the meters offset.

I have not yet look at the excel file - maybe it tells the missing details on what is actually shown.

edit:
 I looked at the Excel file: it shows that the results for the sum error is from 4 readings. It is really surprosing to get that much of an error. This makes me question if maybe a different range is used for the zero readings is used, of something else is going wrong. I would not expect that much of an error in the sum and also not an essentially constant value.

The turn over error also uses 2 zero readings, but this as zero readings at CT CT. This would only correct the offset at the DMM, but add the errors from the relays at the tester. The right type if zero would be GND,GND and DAC,DAC. The is already the factor 0.5 included.

The currected sum error looks odd and for some odd reason it adds up to near zero. I don't understand the idea behind the correction - the compensation is suspiciously good and also super symmetric (not even noise there) for positive and negative, like really removing most real data.

[CurtisSeizert]

The reversal error is calculated as (V(DAC,GND) - V(OS1) + V(GND,DAC) - V(OS2))/2 to give an equivalence between the magnitude of it and that of offset.

The 8 readings are taken together so that the inverse polarity datapoints are done as near in time to the normal polarity ones as possible. This should minimize the error contribution of various drift terms in calculating reversal error.

I should note for anyone looking at the spreadsheet that the headings for the reversal error columns correspond to the binary code of the individual SPDT SW positions. They are in the same order as the first three columns of readings.

The issue I noted with the reversal error for the center tap voltages is that they are about 7x higher on average than the reversal errors for the DAC voltage itself. The averages for the CT reversals are -4.16 and -3.99 uV while those for the DAC are -0.58 uV.  The center tap is buffered, so the output impedance should be the same. I cannot think of a way that this would be from the DUT, but I may be missing something. I am not worried about reversal error for the center tap voltage per se, but if it's indicative of an error with the source that is code dependent, that could lead to spurious conclusions about the higher order coefficients. The good news is that what I would consider the most likely code dependent effect - power dissipation of the nearby divider resistor leading to parasitic thermocouple voltages proportional to P(divider) would be second order. The shape of the CT reversal errors vs. DAC voltage looks very slightly parabolic, but you might have trouble proving that in a court of law.

As for the overall structure of the test, I am trying the option of averaging the results from multiple runs with the individual points taken at 10 NPLC rather than 100. This puts measurements of the individual components for calculating the error terms closer in time. We will see if it helps.