Electronics > Metrology

Remote controlled DMM DCV INL tester based on voltage divider idea

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Heres a circuit suggestion expanding on the idea of a voltage divider being used together with ratio sum math to calculate the INL-curve of the 10V/1V/100mV ranges of a DMM, like done in a manual way here with his LTC2400 by Andreas:

Im pondering wether this method can be made good enough to characterize the INL of a 8.5 digit DMM or rather scratch the 0.1ppm realm, circumventing the need for a known linear calibrator/companion DMM.

Heres a rough description:
-very stable selectable 13V/1.3V/130mV voltage source
-connected to a voltage divider consisting of 14 thermally coupled resistors
-which are individually able to connect the binding posts to any given resistor and therefore voltage with added polarity reversal
-all situated in a milled nice alucase + inner guard case + outer earthed case
-fiber controlled via external µC/PC for lowest EMI
-battery powered for lowest EMI and avoiding CM-errors

With Python for example, it can then be used to compute an INL curve for a given DMM with the underlying math and linear fit shenanigans.

Asking for comments and criticism.  :)


just some annotations:

I would interleave the divider resistors RN?A - RN?H (using neighboured resistors to compensate instead of 2 halves with different temperature)
Typically the X-Capacitor at the common mode choke is larger (> factor 10) than the Y-Capacitors to ground.
I would also use another X-Capacitor on the other side of the common mode choke.
I would use the relay variant if you really have to deal with common mode disturbances.
33uF * 200 Ohm coil resistance may be a bit too low time constant to guarantee 4 ms of the "set current" especially when regarding the ~60 Ohms of the HCT374

Do you plan to do temperature control for better repeatability?

with best regards


This is an interesting idea to measure INL. I would guess Andreas used this to measure the parabolic error function because reversal is not feasible if the voltage range is positive only. I wonder if one could solve for the second order coefficient using reversal and use this method to solve for the third order coefficient. My understanding is you generate some stable voltage Va referred to GND and then check that V(a,GND) + V(ref,a) = V(ref,GND) with the goal of measuring linearity beyond what your voltage source is capable of. It does not seem critical that the voltage source be especially linear since it mostly serves to give you an x-coordinate in the nonlinearity vs input voltage that you are mapping out. Given the cost of just the photoMOS parts, you could probably just build your voltage source using an AD5791 and still come out ahead, though a less expensive DAC, as long as it is stable, should also work. You could imagine using two latching relays to switch the output voltage to check the sum or three to be able to do hands-free reversal.

With this discrete DAC, I would be a bit nervous about the SSRs and thermal EMFs contributing to low frequency noise and increasing the settling time to 0.1 ppm or less. If you are already dissipating the power of running an ADR1000 in this case, I would just put the MCU on the board and control it with an isolated USB to UART using something like an FT230 with some opto isolators. With the long integration times you will need to use to measure sub-ppm INL, a low power MCU will be of little concern for EMI as long as the layout is OK. All it will need to do is drive a DAC, a UART, and a couple GPIOs for relays. I don't think it would be necessary to scale the reference voltages for the DAC to minimize excess resistor noise if you are using something like a DAC81001 as it is 400 nV p-p with an OPA827 buffer with a 10V reference voltage. For battery powered, you could probably skip the case + shield as well, but you will want to be cognizant of the change in power dissipation that occurs over the battery discharge cycle as this can give changing offsets from thermal EMF.

Nice idea, would love to see it built up and testing.

Q. How do you thermally couple 14 resistors, i.e. layout, in order to get an exact thermal affect on the all equally. With 14 I would have thought there would be an element of those towards a centre of some description.


Thanks for the feedback, ill include it in the newer revision schematic.
Im unsure wether it makes sense to interdigitate the RN? network (6.6Vref -> 13.2V) as the dissipation in all resistors is the same. Wont hurt to do that though, as i need to do that for the other networks anyway due to their different resistor dissipation scheme.
The CM-filter wasnt defined yet, ill include your suggestions.
The 33µF relay cap has worked great so far for these relays, so while a bit on the tight side ill continue with this value.

Temp stabilizing the case with a heater should provide added stability, when assuming that the roomtemp variation induced changing TEMF between INL tester and DMM wont completely spoil the increased stability completely.
Im still unsure wether it makes sense to add the heater or rely on alu case thermal capacity.

Some parts are chosen because i bought them once in quantity for quite a bit less than the new price from ebay or similar, thats why i use them here despite the contemporary new price.
In this case these are the OptoFETs, Relays, fiber-converter and i also have some suitably sized milled alu cases which once housed RF-stuff, so in this particular case i use them for best performance.
OptoFETs like PVA3054 have shown small offset voltages in the <100nV-range with low LED drive current in my measurements, though i have to test the AQW210S for this and also the TEMF settling time of single ended switching relay AGQ210A4H.
I roughly get your DAC-idea, but can you draw a schematic of it?
The changing dissipation during battery discharge is something to look out for indeed, thanks.

The 14 resistors consisting of RN3 and RN4, while all dissipating the same power, might also be interdigitated (not yet done in the schematic) to further the thermal coupling via copper traces between them.
As these two networks will however be in separate DIP-cases they might have less statistical equal behavior (TC-ratio) than a single DIP-package with all 14 resistors in it, sitting on the same substrate. Unfortunately theres no 14 resistor network in DIP-package, which i want to avoid pcb swelling induced network instability...though that might be irrelevant given the timeframe of an INL-test...
TDP1601/1401 would be interesting, but Mouser/Digikey dont stock them.


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