I have been playing with a homebrew dual-slope ADC design controlled from an fpga development board. I just realized the on-board oscillator is a mems type. Specifically a Discera 12Mhz MEMS oscillator but without a part number.
I have found alternate design-notes for clocking the fpga using a crystal oscillator. I am considering using something like a HC-49S
http://www.farnell.com/datasheets/1497894.pdf which states a 10ppm freq tolerance and 10ppm freq tempco over operating temperatures.
My questions are -
- I don't have experience with oscillators or crystals. The dev board really only needs enough clock stability for implementing uarts and has probably been built with that in mind. So I suspect that replacing the mems oscillator with a crystal type is an obvious first-step for timing improvement. Is that a reasonable assumption?
- Is it possible to do better for the oscillator - without resorting to ovenized devices which cost hundreds of dollars?
- At first glance, 10ppm freq stability doesn't sound very good - eg. 100uV measurement change over a 10V range. But perhaps the freq stability variation is more like noise and will average out across the duration of the integration interval. And perhaps more importantly cancel out - over the two (run up/down) phases?
- the circuit has the crystal hung across two 27pF caps tied to ground and is fairly typical. Can I just use ordinary ceramics or are NPO types preferred?
- Any ideas for other things to watch in terms of clocking and timebase accuracy?