Today I cut the VCO from IC835 and fed 10.48576 MHz into pin 3 of IC835. Now, all jitter is gone. The force waveforms looks perfect and also the GLUG signals. Only one discrete 200ns timestep was seen on the GLUG signals. But that will correspond to the 5MHz clock.
And what happend to the noise? NOTHING!
I recap what is done until now:
- Power Supplies seems to be ok
- PLL voltage trimmed to 2.5V
- Input chain from bindung posts to the Integrator input seems to be ok -> it should be an ADC problem
- direct signal injection in the ADC shows noise and also Test0 mode -> more arguments for an ADC problem
- IC201 was replaced by a new one
- IC202 was replaced by a new one
- caps were added over IC202 to stabilize power supply
- zener voltage from D204 and D205 is stable
- C201 was replaced with a 100nF MKS -> no change at all
- TR201 and TR202 were swapped with others from others circuits
- TR203 and TR204 were swapped with others from other circuits
- 50Hz mains signal was replaced with 50Hz from signal gen to avoid drifting
- PLL circuit was disabled an 10.48576 MHz was fed in IC835 to remove jitter
There is still more than 10µVpp noise within 60s measurement with 7.5 digits
I think there is not much left to try? Perhaps, IC203, IC204 and IC205
Only these remain in the ADC circuit.