Ultra-high performance solid state relay design

[macaba]

I am contemplating how it would be possible to achieve an ultra-high performance solid state relay.
I could not find any literature detailing what the structure of what such a relay would look like so my best guess is attached as a starting point for discussion.

Approximate requirements:
- 20V capable
- 1mA capable
- <10mOhm ON resistance
- <10pA OFF leakage
- Low thermal EMF
- Low speed, DC (of either polarity, no AC signals).

This seems like the kind of knowledge that resides in people's brains and industry experience, so please let me know any information/suggestions you have (apocryphal or proven!). Before anyone asks... I am aware that mechanical relays exist!

[jonpaul]

use mechanical chopper, or stock CMOS part?

[MegaVolt]

MOSFET+PHOTOVOLTAIC  (FDA217)

[Kleinstein]

The concept can work in principle, but with so many parts in series in the signal path the possible thermal EMF parts can add up.
For the paths to the guards one could take it a little easier with JFET switches. With a limited gate drive signal (some 5 V below the guard signals) the leakage current should be acceptable and less heat.

The combination of 2 MOSFETs and PV optocoupler works, but can create some thermal EMF if not careful in the layout. For low voltage thermal coupling is still OK.
The guard amplifiers may need more than a single OP, as there are not many OPs with well below 1 pA bias suitable for 40 V operation.

I don't see a real need for such a low on resistance - smaller FETs have less leakage to start with.

[Echo88]

I think your specs are achievable macaba.
But i think there are maybe only a handful of COTS solid state relays that would achieve the difficult <0.01R spec.
In my list the AQV252G2S comes close to the required specs, has a bit more leakage than requested and i havent tested its thermal emf. ->
https://www.eevblog.com/forum/metrology/measurements-of-leakage-current-and-offset-voltage-on-some-optofets-and-relays/?action=dlattach;attach=904222
Maybe Omron/Ixys/Panasonic already have a suitable relay for your specs, i was more interested in low leakage ones where the RDSon wasnt critical.

[JohanH]

I use Omron G3VM-41BR. It has following specs:

Max current 7A
Load voltage (peak) 40V
Max resistance 8 mΩ
Max 1 μA leakage

There are also a few other models in the same series, with a bit varying specs.

[macaba]

use mechanical chopper, or stock CMOS part?

Mechanical chopper isn't suitable (e.g. this isn't for nanovoltmeter or chopper amplifier). No stock CMOS parts fit the requirements.

MOSFET+PHOTOVOLTAIC  (FDA217)

Along similar lines to my initial sketch except that a simple implementation like this has too much leakage (hence all the extra circuitry in my sketch).

The concept can work in principle, but with so many parts in series in the signal path the possible thermal EMF parts can add up.

I agree, it's why I wanted separate optocoupler. Then the only consideration is dynamic switching losses that creates heat in the gate. Maybe there are more considerations? Desirable maximum switching frequency is 100Hz but it's likely that this will be less if switching losses causes unacceptable thermal EMF.
About op-amp, I'd probably be looking at AD8641 which maintains acceptable input bias current in 20-50 degC range.
You'll notice that I'm trying to eliminate leakage on both relay terminals as the end application isn't ground referenced on either terminal, hence why there are so many parts.
If this relay is possible then I'm considering a cutkosky divider, that might help you understand the requirement for low RDS on.

But i think there are maybe only a handful of COTS solid state relays that would achieve the difficult <0.01R spec.

I had a look around and some of the COTS SSRs came close to requirements but not quite there. AQV252G2S looks good for a less-demanding requirement.

I use Omron G3VM-41BR.

Thanks, that is a nice part that comes close to requirements. I am concerned about thermal EMF & leakage, I think I may have to measure this part to see how conservative the datasheet is.

[Echo88]

Ahh, Cutkosky, then the low RDSon makes sense.
Regarding thermal EMF: if the TEMF is too big a thermal jumper might be used across the switching contacts to equalize the temperature. https://www.vishay.com/docs/60157/thjp.pdf
I havent measured them regarding leakage current yet though.

Always wanted to see an actual Cutcosky, i only red the description once and how they used many relays to achieve the necessary low switching resistance.

[macaba]

Regarding thermal EMF: if the TEMF is too big a thermal jumper might be used across the switching contacts to equalize the temperature.

That's a neat idea, I'll have to put one of those vishay parts on my electrometer for leakage testing. Yes - I've always wanted to see an actual Cutkosky too, and also wondered what a 21st century variant would look like, hence why I started this thread 

[Kleinstein]

To me the cutkosky divider looks like a slightly odd variant of a R2R DAC. A normal R2R DAC should be a bit easier on the switches. It may take extra effort to keep the load to the reference constant - though not sure how the cutkosky divider handles this.

[chuckb]

Ahh, Cutkosky, then the low RDSon makes sense.
Regarding thermal EMF: if the TEMF is too big a thermal jumper might be used across the switching contacts to equalize the temperature. https://www.vishay.com/docs/60157/thjp.pdf
I havent measured them regarding leakage current yet though.

Always wanted to see an actual Cutcosky, i only red the description once and how they used many relays to achieve the necessary low switching resistance.

I checked the THJP0805AST1 with my K617 - at 10 V and 30 C the leakage current was 35 fa. At 61 C the leakage rose to 300 fa. Very good.
 

[macaba]

To me the cutkosky divider looks like a slightly odd variant of a R2R DAC. A normal R2R DAC should be a bit easier on the switches. It may take extra effort to keep the load to the reference constant - though not sure how the cutkosky divider handles this.

I simulated the self-calibrating Cutkosky [DOI:10.1109/TIM.1978.4314728] vs. self-calibrating R2R ladder (using 2nd ladder for calibration rather than monolithic IC) [DOI:10.1016/S0263-2241(01)00026-4].

1. Load to the reference stays constant in both (that's good).

2. Component count:

(Where N = number of binary bits)
Cutkosky:
6N+4 switches
3N+1 resistors

R2R:
4N+4 switches
6N+4 resistors

8-bit example

Cutkosky:
52 switches
25 resistors

R2R:
36 switches
52 resistors

A similar level of complexity to both (assuming no shortcut; using monolithic IC for current comparison in R2R self-calibration).
The biggest downside (that I've discovered so far) to the R2R is the requirement for a current-to-voltage converter on the output (as per R2R paper), that seems like a source of error.

[DeltaSigmaD]

Though it is late, some comments here to optoelectronic switches such as Omron G3VM-41BR discussed here. I have tested many types of optically-driven MOSFET switches. Thermoelectrical voltages (EMFs) were present at all devices. Other switch parameters were much less critical in my application.
The reason for EMFs is simple: the contact between copper of the PCB and the Si of the MOSFET switch is obtined by a chain of various materials, e.g. Cu to covar or similar to ohmic Si contact to Si. The manufacturers make a good job to balance the EMFs so that they cancel out at the PCB. However, this cannot be perfect in reality as a simple estimation shows:
- the LED has at voltage drop of about 1.1V at 2 mA typ.
- the thermal resistance LED-PCB will be >50 K/W
- the LED is heated by >0.1 K in steady state
- the EMF of one contact chain can be e.g. 400 uV/K mostly caused by the Si
- if we want to get <1uV EMF, the temperature differences along the switch paths must be <2.5 mK

When the LED is switched on or off, a thermal wave is running through switch case. The EMF caused can be measured at a closed switch. The EMF depends even on the off time of the switch.
There are more than one different superposed thermal time constants difficult to be distinguished. I found no algorithm to compensate these EMFs which could be commonly applied.
 

[macaba]

DeltaSigmaD - thank you, that's a nice analysis. Gives me something to think about.

First prototype (PCB has been ordered) of a naive implementation (no guarding, only 2 MOSFETs) will have ‎APV1121SX‎ photovoltiac driver, and PSMN1R4-30YLDX‎‎ MOSFETs. A few other MOSFETs ordered too for leakage testing.

I anticipate that the photovoltiac driver will be some distance away from MOSFETs and that some careful thermal design will alleviate the issue. I'm not entirely sure what careful thermal design that is yet, I could do an aluminium cover over the MOSFETs and ensure that the traces from photovoltiac driver have a chance to equalise temperature with this aluminium cover. On the downside - big metal body near high impedance node? Seems like leakage concern. TBD.

Most MOSFET datasheets contain very little information about sub-threshold leakage, and certainly no information about whether certain process nodes/die design methodologies are suited to low leakage. The aforementioned MOSFET claims: "unique 'SchottkyPlus' technology ... without problematic high leakage current" so that'll be interesting to test. I had some MOSFETs (all have the same 'type' of process/design I think) on my bench so did some testing on those, results attached.

I would like to get some MOSFETs with high Vgs threshold (higher doping in the gate?) to see if that improves the FOM (Figure Of Merit). The FOM I've provisionally come up with is: (10V/Rds-on)/Leakage-at-10V-bias

[ch_scr]

Microchip App Note 1258 has nice pointers with regard to careful thermal design.

[Kleinstein]

I higher threshold would at least help with the sub threshold leakage. However modern MOSFETs tend to be relatively low threshold, while old ones (e.g. BUZ10) have a high threshold, but also relatively large R_on for the size.

The leakage specs are to a large part test limits - actual leakage can be considerably lower.
The gate leakage could to a large part be the protection part. Here it can help if the protection allows a higher voltage (like 20 V) and not just 10 V.

The thermal design seems to have some effect. In my DVM borad I have 2 MOSFET+PV driver type switches. One behaves very good with essentially no detectable offset (< 100 nV, likely < 10 nV), while the other looks like it shows some 500 nV of offest after warm up or the PCB.  relatively tight thermal coupling between the 2 MOSFETs may be helping. A mistake I made was to also have the resistor to limit the PV OK driver relatively close to the PV driver.

With the 3 switch vesion the leakage could be a little less critical, and leakage at very low DS voltage can also be different from leakage at 100 V.

[Echo88]

Do you have some TEMF-numbers for the measured optoelectronic switches DeltaSigmaD?

[JohnPi]

You can further improve sub-threshold leakage by switching the gate to a negative voltage when off. Leakage will reduce by a factor of 10x for each 100-200 mV (depends on FET technology oxide thickness) of negative voltage.

[macaba]

You can further improve sub-threshold leakage by switching the gate to a negative voltage when off. Leakage will reduce by a factor of 10x for each 100-200 mV (depends on FET technology oxide thickness) of negative voltage.

Thanks - I'll try this out as it would certainly be easier to have a 2nd photovoltiac device to provide a very negative gate voltage on a SSR composed of 2 FETs vs. the more complicated/higher part count scheme with guarding that I posted in post #1.

[macaba]

Tried a -9.5V bias (PP3 battery) on the gate, no measurable difference in leakage. Setup wiring details attached. I guess the body diode is the majority leakage source? DUT is SiJA22DP.