T.C. + Hysteresis measurements on brand new LT1027DCLS8-5 voltage reference

[Andreas]

Hello,

just as comparison some measurements from other ADCs (around 7.5 hours):

ADC13, ADC15 and ADC16 are based on temperature compensated AD586 voltage reference.
Allan deviation stays below 0.25uV (after 2:1 divider) or 0.5uV (before divider = 10V range) even for long integration times.

ADC17 carries a LT1236AILS8-5 (also a LS8 SMD ceramic package as LT1027DCLS8-5)
Here the Allan deviation goes up to 2 uV (after 2:1 divider) or 4 uV (before divider) above 200 minutes integration time.

Finally a K2000 and a HP34401A instrument in differential mode
(measuring ~41mV difference of LTZ1-LTZ2 voltage reference in 100mV range).

They start with below 0.1uV (absolute) stability for short integration times.
But go up to 0.5uV for longer measurement times.

So the stability of my AD586 ADCs in 10V absolute range is around that
what can be reached with a 6.5 digit multimeter as differential measurement in 100mV range.

With best regards

Andreas

[Andreas]

Hello,

and here the T.C. adjustment of the 2nd ADC  (ADC#23 with LT1027DCLS8-5#02).
This time with reference soldered on a slotted PCB according to application note. (IMG2446w.JPG from above)

There is a large hysteresis of around 3 ppm. (Measurement of 20160818)
During selection within ADC09 this hysteresis of same reference was much smaller (below 1ppm).
(see measurement 20160622)
So most probably the datasheet spec for the hysteresis is mainly caused by the influence of the PCB board material.

As comparison the "free floating mounted" ADC21 with LT1027DCLS8-5#07. (IMG2447w.JPG from above)
After soldering to the final ADC the hysteresis is still around 1 ppm.
(measurement 20160814).
Similar to the measurement (with wires) during selection in ADC09 (20160703)
and also similar to the selection measurement of reference #2 within ADC09 (20160622)

With best regards

Andreas

[branadic]

There is a large hysteresis of around 3 ppm. (Measurement of 20160818)
During selection within ADC09 this hysteresis of same reference was much smaller (below 1ppm).
(see measurement 20160622)
So most probably the datasheet spec for the hysteresis is mainly caused by the influence of the PCB board material.

This is with the guard trace connected to ground right? Could this be a result of your configuration? Is there a chance to test your setup with the populated resistor divider for the guard?

[Andreas]

Hello,

on ADC23 the guard trace is accidently shorted to the output
which has nearly the same voltage than the NR pin so the
influence should be nearly zero .
(you can see this on the photo IMG2446w.JPG)

I already tried to remove the short during solderin
but I would have to do a complete rework
which again introduces drift to the device.

What I cannot guarantee is that there is no flux residue
under the part with my (mostly hand) soldering method.
I am tinning the device first (with solder wire and enough flux)
and then do a hot air reflow soldering.
Perhaps you have more luck if using special solder paste.

I am more and more convinced that the LS8 package does it not
make easy to get stabilities in the 1 ppm or sub 1 ppm range.

With best regards

Andreas

[Andreas]

Hello,

another hysteresis measurement from the 2nd slotted PCB (ADC24).
This time 5.6 ppm hysteresis (including ageing drift) at 25 deg.
But also this is significantly larger than during wire hook up on ADC9 of the LT1027#17 during reference selection.
(around 2ppm mostly drift).

So for me the influence of the PCB on hysteresis gets systematic.

With best regards

Andreas

[Andreas]

Last but not least

Hysteresis from ADC22: the 2nd dead bug (in hole) mounted LT1027.
Here the hysteresis is below 0.5ppm at 25 deg C.
During selection of LT1027#03 within ADC09 there was also a large ageing drift.
(so drift + hysteresis around 2 ppm).

With best regards

Andreas

[branadic]

How can you be sure that desoldering and resoldering hasn't change the conditions of the LT1027LS8?

[Andreas]

Hello branadic,

I have here the fact that on 2 samples (with dead bug style mounting)
the hysteresis has not changed (even with some soldering).

Of course I have some drift of the output voltage between the measurements before and after.

On the 2 samples with slotted PCB the hysteresis is increased significantly.
So I see a good correlation (of course no proof) between mounting and hysteresis.

Do you have different experiences?

With best regards

Andreas

[branadic]

Do you have different experiences?

No, I'm just thinking loud

[Andreas]

Hello branadic,

it´s often good too ask some questions.
There is a risk for getting blind for the things I do as a habit with my ADC´s.

This week someone  asked me about the discrepancy of the decoupling capacitor for the LTC2400 and the LT1027.
In LTC2400 datasheet a 100nF ceramics and a 10uF Ta is recommended.
In LT1027 datasheet either a 4.7 uF or no decoupling capacitor at the VREF output is recommended.
The LT1027 datasheet tells that with a 100nF capacitor the output ringing will be a maximum.

In my cirquits I use 100nF and 10uF as a habit (for critical debouncings).
The intention here is that the 10uF Ta with its ESR of around 2 Ohms acts similar to a snubber network (Boucherot)
to dampen any oscillations created by a ceramics capacitor (with wire inductivity).

But after the question I was not shure: will this work in any case and also with the LT1027?

-> I had to check this.
I tested 3 different configurations together with ADC24 (slotted PCB).
VREF1: 100nF X7R + 10uF Ta Size A (initial configuration)
VREF2: 10uF Ta alone
VREF3: 100nF X7R
VREF4: same as VREF1 (after all changes)

The 10uF Ta is a RS-components 684-4443 http://de.rs-online.com/web/p/tantal-elektrolytkondensator/6844443/

I measured VREF with a 200 MHz BW (+10:1 probe with 250 MHz BW)
oscilloscope with short connection to the D-Sub connector (see photo)
to see any oscillations of the reference.
In parallel I measured LTZ#4 via 2:1 divider with the ADC.

First surprise: there are large spikes (200-300 mVpp) with risetimes in the 2-3 ns region
 (near the BW-limit of the scope = 2 ns) from the internal 153 kHz clock of the LTC2400.
This is something that I never expected from a analog cirquit.

To the scope pictures:
Overview shows the first 5 ms of the conversion.
There is a large first spike (start of conversion) followed by some smaller spikes
on each edge of the 153 kHz clock (mostly switching noise of VREF input).

Zoom 500x10 (x = 500 y = 10) shows the conversion clock.
VREF3 (100nF alone) shows large oscillations between the clock.
The other configurations do not differ much.

Zoom 10k (x = 10000) shows a single edge of the conversion clock.
The ringing is for the 10uF and 10uF + 100nF configuration
shorter than the 460ns datasheet spec.

So from the scope pictures there is not much difference between the
10uF and the 10uF + 100nF configuration.
The maximum spike amplitudes seem to be 3-5% smaller with the
combination of the capacitors.
On the 100nF alone configuration the ringing is clearly visible.
(see also table).

The comparison of the ADC24 readings shows a factor 2-3 increased uVpp noise for the 100nF alone capacitor.
The readings of the LTZ#3 are also increased by 170 uV (=47ppm) in VREF3 against the VREF1 configuration.
But also the VREF2 configuration (10 uF alone) has a increased reading of 7.5 ppm against VREF1 configuration.
So which one is nearer on the truth?

This gets clearer when measuring the own 5V reference through the 2:1 divider on the ADC input.
In this case the theoretical reading should be exactly 2500 mV.
In practice there is some loss in the 2:1 divider (which can be seen by the HP34401A high impedance measurement).
The actual value is around 20uV or 7.6 ppm lower than the half value.
So the nominal reading in this case should be 2499.981 mV.
VREF2 is +9.7 ppm too high
VREF3   +30.5 ppm  and
VREF4 is -3.5ppm (low)

I not really thought that the decoupling capacitor influences the readings (INL)
that much regarding the dynamic resistance of the VREF in the mOhm range.
So there is shurely room for some improvement by the right placement and value of the decoupling capacitors.

with best regards

Andreas

[Kleinstein]

This is really quite some spikes on the reference voltage. The spikes are also really fast - so the layout might be important too. The LTC2400 does not have many pins, so there could be also some interaction with the decoupling of the supply and ground, not only the reference input.

I am also surprised to see such fast signals with a supposedly slow and low power ADC. So we have to expect even worse trouble with something like the LTC2440  - though at least they have separate differential inputs and not everything to one poor GND pin.

I like the idea of damping through the ESR of the Ta cap, but I think the ESR is to low for this - the impedance of lines is more in the 30-150 Ohms range.

[branadic]

What about setting up a pi-filter using a resistor or inductance such as a ferrit bead?

[Andreas]

Hello,

@branadic: how exactly? every Ohm between reference output and VREF pin on the ADC will degrade INL according to data sheet when having a large (>10nF) capacitor on the ADC VREF pin side.

Perhaps the cleanest solution would be to make a voltage tracker (TLE4250G?) for the VDD pin and connect VREF directly with either a small (1nF) capacitor directly or via a resistor to the reference.

Other thoughts are to have perhaps a additional 1uF foil capacitor to deliver more energy to the ADC and reduce the amplitude of the spikes.

@Kleinstein: I do not think that the line (2-3 cm) is long enough to have a line impedance.
It is more a small inductivity which generates a resonance with the high Q ceramics capacitor.

With best regards

Andreas

[Kleinstein]

In the pictures above I could see the caps at the reference voltage, but not the caps at the supply. So troublesome spikes could also depend on the supply decoupling. I would expect similar spikes there too, maybe even more.

From the scope pics is looks like ringing is at something like 20 MHz. With a 100 nF cap this would be a resonance in the 1 nH range, which is rather low for something like 3-4 mm. So it could be there is a different part resonating, not the 100 nF cap and a short piece of wire.
If it is the 100nF and an inductance resonating, impedance would be in the 1 Ohms range (Q / C/ omega). Q here is the quality factor of the ringing. So the 3 Ohms ESR of the Ta cap might be not that bad.

At this speed a 1 µF foil cap could be tricky, as it is large and thus can not be that close to the chip.

On the positive side, a foil cap would be less temperature dependent. As long as the ringing is constant, it might not be that bad. The big trouble could happen if it changes a lot with temperature.

[branadic]

First of all, I guess you are refering to Figure 25. INL Error vs RVREF (Large C) with your combination of 100nF and 10µF? I have a few problems interpreting the diagram shown. It seems that there is no difference between 1µF and 10µF?
So LTC2400 should work with 4.7µF without problems in INL? On the other hand the datasheet say's:

"...If the external capacitance is large (CVREF > 0.01µF), the linearity will be degraded by 0.15ppm/? independent of capacitance at VREF, see Figure 25..."

So what is the truth?

On the other hand a 4.7µF to ground for the LT1027LS8 followed by a ferrit bead with low series resistance for decouling followed by the combination of 10µF and 100nF for the LTC2400 could do the job?

[Andreas]

Hello,

In the pictures above I could see the caps at the reference voltage, but not the caps at the supply. So troublesome spikes could also depend on the supply decoupling. I would expect similar spikes there too, maybe even more.

in this case the VREF and supply are tied together like in many application notes (the LTC2400 needs nearly no current).

From the scope pics is looks like ringing is at something like 20 MHz. With a 100 nF cap this would be a resonance in the 1 nH range, which is rather low for something like 3-4 mm. So it could be there is a different part resonating, not the 100 nF cap and a short piece of wire.

The ringing that I measure is in the 8 ns-range period time. (120 MHz).
(pictures 10k zoom are 50 ns / div) (500us/div / zoom = 10000).
This makes it even more mysterious.
On the other side: Inductivity also depends on the loop area between the wires and can go down to 0.2 nH/mm in a practical 2-layer PCB layout.

For the 1uF: there should be room for a WIMA SMD capacitor (PPS-series) on the other side of the PCB.
with best regards

Andreas

[Andreas]

First of all, I guess you are refering to Figure 25. INL Error vs RVREF (Large C) with your combination of 100nF and 10µF? I have a few problems interpreting the diagram shown. It seems that there is no difference between 1µF and 10µF?
So LTC2400 should work with 4.7µF without problems in INL? On the other hand the datasheet say's:

"...If the external capacitance is large (CVREF > 0.01µF), the linearity will be degraded by 0.15ppm/? independent of capacitance at VREF, see Figure 25..."

So what is the truth?

On the other hand a 4.7µF to ground for the LT1027LS8 followed by a ferrit bead with low series resistance for decouling followed by the combination of 10µF and 100nF for the LTC2400 could do the job?

Hello branadic,

yes I refer to the diagram 25.
And also there is no difference between 1uF and 10uF except of the ESR if using Ta.
When I started my first design the 10uF Ta caps had 6 Ohms.
The latest Ta size A now have 1.7 Ohms.
And at those high frequencies which are generated by the LTC2400 the
LT1027 might be too far away to contribute to the current spikes.

The truth might be anywhere in between.
Fact is that I measure a difference in INL (2:1 own reference) depending
on the capacitors populated while having the same PCB layout and LT1027.

with best regards

Andreas

[Kleinstein]

With such a high frequency, it is possibly that even the small loop at the probe could pick up the ringing. At least the amplitude and waveform could be different.

The supply current is low, but there are current spikes at both the reference input and at the supply pin. So separate supply and ref. decoupling might be a good idea. However there is only one GND pin - so they are coupled anyway. From the shown internal circuit, I would not expect a really large spike at the reference input - a large spike from the supply input in more what one expects. So my best guess would be to have separate decoupling for the reference and supply, with a filter (e.g. ferrite) for the supply. However this could be tricky to impossible with the existing PCB.

The INL is influenced by the combination of resistance and capacitance. A high capacitance is a problem, when there is a resistance at the reference. With reference and supply tied together, there could be an additional error from the supply current - not much, but it also does not need a lot to drop the supply a few ppm. So in this case a very low impedance for V_ref = V_supply is needed. I am not sure about the frequency of the impedance that is relevant. Like a linear voltage regulator, the output impedance of the LT1027 reference should be rather inductive over a wide range. This should be more of a problem than the few cm in between.

[Andreas]

Hello,

a comparison of some measurements on ADC21 (LT1027DCLS8-5 reference dead bug in hole mounted)
and ADC24 (LT1027DCLS8-5 mounted in slotted PCB) after all adjustments are done:

Both devices hooked up in parallel on LTZ#4.

on 14.09.2016 and 17.09.2016 T.C. measurement of the resulting T.C. after 3rd order correction
(and to show the resulting drift of the temperature cycles).

ADC21 deviation is below 1 ppm (although there is some ageing drift during cold phase on 17.09.)
ADC24 deviation is around 6 ppm (20 uV / 3.6V) most of it is hysteresis influence due to the PCB.

Both devices show a rather large ageing drift within the 3 days.
I hope that this will reduce during the next few kHrs.

on 15.09.2016 offset temperature drift of the ADCs (input shorted).
This checks mainly the LTC2400 drift and the buffer op-amp of the 2:1 capacitive divider.
ADC21 has LTC1050 and  16 nV/K (0.5 uV after 2:1 divider from 15 .. 40 deg C)
ADC24 has LTC2057 and -41 nV/K (1uV after 2:1 divider from 15 .. 40 deg C)

on 16.09.2016 2:1 divider input shorted to own VREF.
this checks gain drift of the capacitive divider at half input range (VREF drift cancels out).
ADC21 -28 nV/K
ADC24 -61 nV/K

with best regards

Andreas

[branadic]

So what's the conclusion?
I guess there is a need to find and investigate different assembly technologies such as flexible circuit boards made of polyimid or semiflexible circuit boards made of thin FR4 to build up such sensitive devices, as long as dead bug technics isn't the way you want to go, even in a commercial product.
Also a ceramic substrate with a single sided lead frame could be a solution, carrying all necessary passives.
Maybe we can find further ways of connecting such a device to a board?

[EmmanuelFaure]

Andreas, by any chance have you measured at least one LT1027's drift since you began to test them?

[acbern]

This reference is rated appr. 30ppm/1000h for the H package (hermetic, but no longer available), so the standard plastic package drift will be even more. This is not a low drift reference, working on dead bug mounting analysis or so is not worth it (except as for an excercise), the drift fluctuations peces to pice will probably be more. For low drift optimization, a burried zener in an hermetic case is inevitable.

[Alex Nikitin]

This reference is rated appr. 30ppm/1000h for the H package (hermetic, but no longer available), so the standard plastic package drift will be even more. This is not a low drift reference, working on dead bug mounting analysis or so is not worth it (except as for an excercise), the drift fluctuations peces to pice will probably be more. For low drift optimization, a burried zener in an hermetic case is inevitable.

Hmm, the LT1027DCLS8-5 is a buried zener reference in a hermetic case  .

Cheers

Alex

[acbern]

True, wrong device, my mistake. And it is only 12ppm/18ppm at 1/3khr.

[Andreas]

Hello,

from my measurements with plastic DIP devices I know that the LT1027 chip itself has very good features.
The only problem with PDIP package is humidity sensitivity.

When I calibrate it out (with a filtered time constant of around 3-5 days) I get relative stable measurements.
Of course the rH cannot be completely canceled out since the behaviour is probably non-linear.
On 2 well pre-aged devices (ADC4 + ADC8) I measured around 0.5ppm/%rH and a yearly (average) drift of 1-2 ppm per year.
So the values in the older datasheets are probably very conservative.

@branadic: it is too early to get a final conclusion.
PCB-mounting is critical but perhaps the hysteresis gets smaller with a smaller temperature gradient.
The 0.12 deg C/minute or 7.2 deg C per hour is somewhat high even in my "lab".
I think 2-3 deg C per hour is more realistic.
Some day I will do a further test with reduced ramp speed.

@Emanuel: I have stored all measurement values. But partly with different LTZ references and with different ADCs between selection and final build (different gain and INL). And between the steps soldering of wires to the reference, removing wires and again soldering to the PCB. So each step has its own ageing drifts. I dont know if it makes really sense to calculate any drift with all these treatments.
At the moment I do some drift measurements of all 4 ADCs in parallel and without temperature cycling (except for changes in room temperature).
Perhaps I will see more in a few hundreds of hours.

with best regards

Andreas

Edit: have forgotten  to add the drift  chart of ADC4 + ADC8 (LT1027 in PDIP package).
In the chart are the original measurement values LTZ#1 (thin lines) on the left side (with 2:1 divider)
together with filtered RH-value (thin line green) scale on the right side
(unfortunately in rH instead of rH % so a factor 100 in between)
on the X-Axis: days with zero = last calibration.
The dotted points are the corrected values (with rH correction).
The imperfect correction shows that the modeling of rH soaking with a averaging filter over 5 days is not perfect.