Time interval measurement limits

[jonpaul]

Hello again,

1/ Wavecreest: 1990s diansaurs, cant get them runnong, used old windows I recall.

2/ I never saw or used the comparisons you make re jitter.

The accuracy of PERIOD depends on the REF clock of the scope or analyzer. Never an issue!

The jitter is a statistical number derived from a period sample set.

The resolution is the minimum increment in a jitter measurement, eg a histogram is 100 pS in TA320 and 25 pS in TA720.

Sub pS measurements are best researched at your local Swiss facilities:

CERN near Genève and ETH in Zurich also Zurich Instruments.



Kind Regards,

Jon

[David Hess]

Nice overview presentation from CERN (2008): https://indico.cern.ch/event/43741/contributions/1924510/attachments/939372/1332084/TIMMethods.pdf

Paper it is based on (2004): https://ztc.wel.wat.edu.pl/met4_1_004.pdf

So the methods very briefly:

- Coarse counting / periodic function sampling: counting the number of pulses inside the event, straightforward method, resolution can be improved by random sampling (e.g. sampling scope) and averaging

- time stretching then counter: I dont know any device

- time to amplitude then ADC: Yokogawa TA series, SR 620

- Vernier method: HP 5370A

- Tapped delay line: HP5371A, jTDC project mentioned before

There are some numbers on the paper about their resolution etc. but not sure what the current state-of-art is, I should find a recent paper.

Bruce from the Time-Nuts email list has a page which describes the major methods.  Modern DSOs with "digital triggering" use transition midpoint timing and no separate trigger circuit path.  Old DSOs use dual slope/ramp because they had no requirement for faster operation.

- how is the jitter noise floor of a scope measured ? with a much lower phase noise oscillator, so whatever seen is the noise ?

That is right.

- if a low phase noise external ref clk is provided to the scope, is the jitter noise floor also decreased ?

No, because the much faster internal sampling clock is phase locked to the external reference, so only long term jitter is improved.

[edpalmer42]

1/ Wavecreest: 1990s diansaurs, cant get them runnong, used old windows I recall.

Depends on what you want to do.  For frequency and time interval measurements, the DTS 2050/2070 series are supported by Timelab so data collection is painless if you have GPIB.  The data can be exported for use in other programs.

While reading the manual for my DTS-2077, I came across the section on "strobing voltmeter" and realized it could be used as a subsampling scope with a 100 Gsps equivalent sampling rate.  I threw together a *very* crude proof-of-concept program and captured the data shown in the attached graph.  The X-axis is units of 100 ps.  The Y-axis is volts.  There are various limitations (trigger, memory, etc.) so I don't know if it's actually practical to use the beast as a scope.

Ed

[maxwell3e10]

Carmel Instruments makes PXIe time interval analyzers that have single edge jitter of about 2psec rms https://www.carmelinst.com/products/counters-time-interval-analyzers

[metebalci]

Bruce from the Time-Nuts email list has a page which describes the major methods.  Modern DSOs with "digital triggering" use transition midpoint timing and no separate trigger circuit path.  Old DSOs use dual slope/ramp because they had no requirement for faster operation.

Great, thanks

- how is the jitter noise floor of a scope measured ? with a much lower phase noise oscillator, so whatever seen is the noise ?

That is right.

OK nice, I will soon have a low phase noise oscillator, I will try to see which one has lower noise.

- if a low phase noise external ref clk is provided to the scope, is the jitter noise floor also decreased ?

No, because the much faster internal sampling clock is phase locked to the external reference, so only long term jitter is improved.

Maybe it is difficult to answer briefly but can you tell why only the long term jitter is improved ? or where can I look ? I ask because I thought PLL transfers some portion of the phase noise of the reference to output, so why there would be no change here ?

[David Hess]

Maybe it is difficult to answer briefly but can you tell why only the long term jitter is improved ? or where can I look ? I ask because I thought PLL transfers some portion of the phase noise of the reference to output, so why there would be no change here ?

The PLL combines the noise spectrums based on its breakpoint frequency, which is necessarily below its Nyquist frequency.  So the phase noise and jitter can only be improved at lower frequencies where the PLL is influencing the output, which only affects long term jitter.  Of course if it is long term jitter that you want to improve, then that is well worthwhile.

Measuring the jitter will likely involve a low phase noise crystal oscillator while the DSO is relying on a PLL multiplied VCO so it should not be difficult to find a difference.  You might remember a couple years ago where the Rigol DS1000Z series was revealed to have problems with very high jitter at low frequencies because of a design error in its PLL.

[metebalci]

Maybe it is difficult to answer briefly but can you tell why only the long term jitter is improved ? or where can I look ? I ask because I thought PLL transfers some portion of the phase noise of the reference to output, so why there would be no change here ?

The PLL combines the noise spectrums based on its breakpoint frequency, which is necessarily below its Nyquist frequency.  So the phase noise and jitter can only be improved at lower frequencies where the PLL is influencing the output, which only affects long term jitter.  Of course if it is long term jitter that you want to improve, then that is well worthwhile.

Measuring the jitter will likely involve a low phase noise crystal oscillator while the DSO is relying on a PLL multiplied VCO so it should not be difficult to find a difference.  You might remember a couple years ago where the Rigol DS1000Z series was revealed to have problems with very high jitter at low frequencies because of a design error in its PLL.

I realized I was mistaken in something in how PLL works. Many thanks David.

[metebalci]

Carmel Instruments makes PXIe time interval analyzers that have single edge jitter of about 2psec rms https://www.carmelinst.com/products/counters-time-interval-analyzers

Another cool device, I didnt find info about how it exactly works

[1audio]

RE HP5370  The resolution floor is 20 pS https://www.febo.com/pages/hp5370b/

[Echo88]

TAPR-TICC:
https://github.com/TAPR/TICC 60ps resolution open source counter
https://tapr.org/product/tapr-ticc/

[metebalci]

TAPR-TICC:
https://github.com/TAPR/TICC 60ps resolution open source counter
https://tapr.org/product/tapr-ticc/

Thanks. I did not know there are TDC ICs like the TI one used in this project.

[metebalci]

This IC TDC7200 is pretty nice. I made a small prototype to measure the time it takes to set two GPIO lines to high immediately one after other on a RPi, and it works flawlessly. I think the error is around ±50ps assuming the external clock is good enough.

For example:

# of measurements: 10000
mean: 31.51 ns
sigma: 2.23 ns
min: 7.89 ns
max: 139.93 ns
median: 32.17 ns

[hgl]

Can you show us exactly what you did ?
 

[metebalci]

Can you show us exactly what you did ?

I mounted the IC on a DIP adapter and put on the breadboard, connected the SPI and other relevant lines (ENABLE, INTB, TRIGG, START, STOP) to a RPi. I am powering both from a power supply (5V for RPi, 3.3V for TDC), and using the waveform generator of the scope for CLOCK at the moment. I tried 2MHz and 5MHz for the CLOCK, both works fine, 10MHz is not working, I guess because of the breadboard. I wrote two programs on RPi, one for measuring (tia), one for device simulation (dut).

I checked some measurements with the scope and they are roughly correct.

I uploaded the programs here: https://github.com/metebalci/tdc7200_demo

[Leo Bodnar]

While reading the manual for my DTS-2077, I came across the section on "strobing voltmeter" and realized it could be used as a subsampling scope with a 100 Gsps equivalent sampling rate.  I threw together a *very* crude proof-of-concept program and captured the data shown in the attached graph.  The X-axis is units of 100 ps.  The Y-axis is volts.  There are various limitations (trigger, memory, etc.) so I don't know if it's actually practical to use the beast as a scope.

What's the risetime of this pulse source?
Leo

[edpalmer42]

While reading the manual for my DTS-2077, I came across the section on "strobing voltmeter" and realized it could be used as a subsampling scope with a 100 Gsps equivalent sampling rate.  I threw together a *very* crude proof-of-concept program and captured the data shown in the attached graph.  The X-axis is units of 100 ps.  The Y-axis is volts.  There are various limitations (trigger, memory, etc.) so I don't know if it's actually practical to use the beast as a scope.

What's the risetime of this pulse source?
Leo

It's a 74AC04 inverter.  I don't know what the risetime is speced at.  The only spec the datasheets give is propagation delay.  I paralleled two gates and included a resistive attenuator to reduce the output voltage while still providing a 50 ohm source impedance.  It's intended use is to connect to a Wavecrest DTS-2077 which has a maximum input voltage of 1V2 and, I think, a damage level of 1V7.  The resistive attenuator keeps even the open-circuit voltage to a safe level.

Ed

[Leo Bodnar]

The X-axis is units of 100 ps
....

It's a 74AC04 inverter.  I don't know what the risetime is speced at.  The only spec the datasheets give is propagation delay.  I paralleled two gates and included a resistive attenuator to reduce the output voltage while still providing a 50 ohm source impedance.  It's intended use is to connect to a Wavecrest DTS-2077 which has a maximum input voltage of 1V2 and, I think, a damage level of 1V7.  The resistive attenuator keeps even the open-circuit voltage to a safe level.

Ed

Oh, so the whole chart is 1300 x 100ps = 130ns, correct?  10/90 risetime then looks like about 2ns?

Leo

[edpalmer42]

The X-axis is units of 100 ps
....

It's a 74AC04 inverter.  I don't know what the risetime is speced at.  The only spec the datasheets give is propagation delay.  I paralleled two gates and included a resistive attenuator to reduce the output voltage while still providing a 50 ohm source impedance.  It's intended use is to connect to a Wavecrest DTS-2077 which has a maximum input voltage of 1V2 and, I think, a damage level of 1V7.  The resistive attenuator keeps even the open-circuit voltage to a safe level.

Ed

Oh, so the whole chart is 1300 x 100ps = 130ns, correct?  10/90 risetime then looks like about 2ns?

Leo

Correct.  If not for the wiggles at the top, risetime might have been < 1ns.  Most annoying!    However, I set my trigger voltage to about 0V25 to get the best slew rate so the wiggles aren't an issue.

Ed

[hgl]

[quote

This IC TDC7200 is pretty nice. I made a small prototype to measure the time it takes to set two GPIO lines to high immediately one after other on a RPi, and it works flawlessly. I think the error is around ±50ps assuming the external clock is good enough.

For example:

# of measurements: 10000
mean: 31.51 ns
sigma: 2.23 ns
min: 7.89 ns
max: 139.93 ns
median: 32.17 ns

Can you show us exactly what you did ?

I mounted the IC on a DIP adapter and put on the breadboard, connected the SPI and other relevant lines (ENABLE, INTB, TRIGG, START, STOP) to a RPi. I am powering both from a power supply (5V for RPi, 3.3V for TDC), and using the waveform generator of the scope for CLOCK at the moment. I tried 2MHz and 5MHz for the CLOCK, both works fine, 10MHz is not working, I guess because of the breadboard. I wrote two programs on RPi, one for measuring (tia), one for device simulation (dut).

I checked some measurements with the scope and they are roughly correct.

I uploaded the programs here: https://github.com/metebalci/tdc7200_demo

The Tdc7200 cannot measure under 12ns. You need a stable frequency and a stable start/stop difference.  I made measurements 3 years ago with a 10MHz OCXO, 2 TDC7200 in parallel and a CPLD that generates one start and 5 stop pulses with 100ns interval each and got similar results as TAPR/TICC.

[metebalci]

[quote

This IC TDC7200 is pretty nice. I made a small prototype to measure the time it takes to set two GPIO lines to high immediately one after other on a RPi, and it works flawlessly. I think the error is around ±50ps assuming the external clock is good enough.

For example:

# of measurements: 10000
mean: 31.51 ns
sigma: 2.23 ns
min: 7.89 ns
max: 139.93 ns
median: 32.17 ns

Can you show us exactly what you did ?

I mounted the IC on a DIP adapter and put on the breadboard, connected the SPI and other relevant lines (ENABLE, INTB, TRIGG, START, STOP) to a RPi. I am powering both from a power supply (5V for RPi, 3.3V for TDC), and using the waveform generator of the scope for CLOCK at the moment. I tried 2MHz and 5MHz for the CLOCK, both works fine, 10MHz is not working, I guess because of the breadboard. I wrote two programs on RPi, one for measuring (tia), one for device simulation (dut).

I checked some measurements with the scope and they are roughly correct.

I uploaded the programs here: https://github.com/metebalci/tdc7200_demo

The Tdc7200 cannot measure under 12ns. You need a stable frequency and a stable start/stop difference.  I made measurements 3 years ago with a 10MHz OCXO, 2 TDC7200 in parallel and a CPLD that generates one start and 5 stop pulses with 100ns interval each and got similar results as TAPR/TICC.

I know the minimum is 12ns in mode 1, this is just a simple -is it working- setup naturally not aiming to reach 50ps resolution on breadboard. TAPR/TICC is I believe running in mode 2 which has minimum 250ns. 

[hgl]

12 ns are the minimum time between start and stop signal and is mode independent. TICC runs in Mode 2 and a minimum of 300 ns TOF.

My minumum is 100ns TOF in Mode 1. And the course counter  I had chosen 5 stop pulses because I thought I could average them. The longer the times become the more scattered the results and you do not get a higher resolution.

There is also the AS6501 with 2 channels, which claims 10ps resolution. I have ordered 2 for testing.

[metebalci]

12 ns are the minimum time between start and stop signal and is mode independent. TICC runs in Mode 2 and a minimum of 300 ns TOF.

My minumum is 100ns TOF in Mode 1. And the course counter  I had chosen 5 stop pulses because I thought I could average them. The longer the times become the more scattered the results and you do not get a higher resolution.

There is also the AS6501 with 2 channels, which claims 10ps resolution. I have ordered 2 for testing.

The minimum interval in recommended conditions in the datasheet is different for modes, 12ns vs. 2xTclock. Maybe 12ns also works even if no clock rise happens in mode 2 but even if it is the case it doesnt look like it is recommended.

I will check AS6501, thanks for mentioning.

[David Hess]

Some time interval measurement methods have difficulty measuring very short periods, so they have a minimum pulse width which is much greater than their resolution.  On a digital storage oscilloscope this is not a problem because the trigger can be compared to a later sampling clock edge.

This can be worked around in the design, and negative time can even be measured, but it is tricky.