Transmille 8081 ADC

[rigrunner]

I was the unfortunate winner of the broken Transmille Fisherprice 8081 that was listed on ebay some time ago. 
Long story short is that something unwise was done with the input that  vaporised part of the input circuitry and PCB.  The +15v regulator was burnt short circuit which fed -15V & +25V unreg to everything on the -15V & +15V rails. Toasty   



Spot the difference?

I eventually got the thing running and giving readings but wasn't happy enough with it to make any posts here about it.

Transmille sometimes respond to messages placed on their system regarding the 8081, but aside from a brief exchange of useful messages with Martin Cox they show little to no interest in support. They won't release any diagrams or service details and they ignore requests to purchase spare parts from them.

I've still got more work to do on it, but I've finally gotten around to do something I have had in mind for a while. Reverse engineering the ADC board.
Please bear in mind that I haven't reverse engineered a complete board for anything before, so there will be errors.


Here's my attempt.

[ Specified attachment is not available ]

I'm thinking about making another ADC PCB because the reference voltages run through a silly number of vias, quality of the original really isn't great and all of my hacking about has taken its toll.

I think I can delete IC16 by using the unused /2 in IC14 in the remake. Comments, fixes and suggestions for changes in the remake are welcome.


Edit: fixed unannotated diodes and duplicated resistor numbers.
 

[TiN]

Would be interesting to see high res photos of the boards (all, not just ADC) of the unit for education purposes. Not very popular unit out there.

[mendip_discovery]

I had one of these in a lab I used to work in, never used it much. I remember that it was still rather experimental when they had it, but the lab manager never knew how to use it. Of the times I touched it I just referred to it as a random number generator, the last 4 or 5 digits were always jumping about. This was before I got my VoltNut and started to hunt for better readings. I left the lab about only a year and a half.

I did have some stuff from Tansmille about it, I will see if I can find it.

[Kleinstein]

The ADC looks quite similar to the mark-space ADC of the older Solartron 7081 and similar. The counter part went to the µCs, though still quite a bit discrete logic left.

Much of the parts look like standard parts. So they could be replaced if needed. Some of the OPs may have well survived a -15 and +25 V operation.


Running the reference through many vias should not be a issue - the voltage of 10 V is relatively high and thus a low µV range of largely constant thermal EMF there should be no real problem.

There are other points that can be more important than that:
It starts with having 3 separate crystalls that can and will interact in some way. Ideally they would rund in sync and things may be OK - but chances are they are not that equal and would synchonize to a different ratio, ausing trouble on the beat frequency. The creation of the +-10 V reference would be quite important. The buffering of the reference would also be a mayor issue. With long traces there can be RF range issues and some length may even be a good thing, though more a source of trouble.
Anyway with 2 µCs with internal flash memory it would be hard to duplicate the board without reusing these chips.

The ADC type has principle limitations. So it would likely not be low noise, no matter what. A principle limitiation is that is needs a realtively stable input signal and switching the input would be slow - it may need some 10-100 ms to recover, before giving a stable reading. So a fast auto zero cycle is not an option and ADC drift would thus be an issue. At best I would see it comparable to the Solartron - more like lower grade.

It could still be good INL for very long integration times, if everything else is done right.
With the PLL chip there is still a chance to get some interference, so good INL is by no way guaranteed.

[rigrunner]

Would be interesting to see high res photos of the boards (all, not just ADC) of the unit for education purposes. Not very popular unit out there.

There isn't much more to see over the pictures your have on xdevs.
Is there anything in particular you want to see?

[rigrunner]

Of the times I touched it I just referred to it as a random number generator, the last 4 or 5 digits were always jumping about.

This wasn't the most stable measurement in it's original form.
Transmille do something odd with the 50Hz sync that causes noise. The original code in the 18F252 timing pic switches on the UART TX and feeds it to IC11 where it mixes and offsets the zero crossing. Not to mention that when the IC11 output transistor switches to ground, shorting out the UART, it introduces > 10mV of noise on the 5V rail.

Switching off the UART and swapping the inputs to IC11 reduces noise a LOT.

[rigrunner]

Some of the OPs may have well survived a -15 and +25 V operation.

A couple did survive, but not many. All of the muxes went low resistance and drew enough current to blow fuses.  The LTZ IC went thermonuclear and melted the foam insulation around it.

Running the reference through many vias should not be a issue - the voltage of 10 V is relatively high and thus a low µV range of largely constant thermal EMF there should be no real problem.

There are other points that can be more important than that:
It starts with having 3 separate crystalls that can and will interact in some way. Ideally they would rund in sync and things may be OK - but chances are they are not that equal and would synchonize to a different ratio, ausing trouble on the beat frequency. The creation of the +-10 V reference would be quite important. The buffering of the reference would also be a mayor issue. With long traces there can be RF range issues and some length may even be a good thing, though more a source of trouble.

I can rework the 10MHz in the remake. Single crystal through a buffer?

The reference is a datasheet copy circuit with the LTZ1000CH package mounted inverted on the PCB.
2 x OP177 generating main 10V/-10V Vref and 2 x OP27 in unity gain providing 10V/-10V buffered Vref.
The reference is a good 30cm away from the ADC. I have considered moving it to the ADC board

In the attached case image the red and blue lines are the +10V/-10V reference voltage path, and the green line is the path for the reference 0V
 

Anyway with 2 µCs with internal flash memory it would be hard to duplicate the board without reusing these chips.

I have copied the PIC micros.

The ADC type has principle limitations. So it would likely not be low noise, no matter what. A principle limitiation is that is needs a realtively stable input signal and switching the input would be slow - it may need some 10-100 ms to recover, before giving a stable reading. So a fast auto zero cycle is not an option and ADC drift would thus be an issue. At best I would see it comparable to the Solartron - more like lower grade.

It could still be good INL for very long integration times, if everything else is done right.
With the PLL chip there is still a chance to get some interference, so good INL is by no way guaranteed.

The last pieces of the puzzle (VHP202) will hopefully be on the way to me shortly. If all works out as planned I'll log some measurements and post results.

[guenthert]

Thanks for the ADC schematic.  Perhaps I'm looking at an older drawing (Ref 1), but I'm pretty sure that R6 is connected to (some) GND, much like R5 (R6, R20 forming a voltage divider, much like R5, R11).  Further, I have a hard time believing that there shouldn't be any DC feedback for IC1, IC2. 

[Kleinstein]

NO direct feedback at IC1 / IC2 is correct, this is an 2 OP integrator with IC1 for the low frequenccies and IC2 for the higher frequencies.
The DC feedback comes via the reference switching. Any direct DC feedback would cause INL errors, so there may be extra guard-traces to avoid it.


If one would really respin a PCB for the ADC here are a few points to consider:
For the clock, my favorite would be a single canned oscillator and than maybe (but not absolutely needed) extra buffers / level shifters.

I would consider a little low pass filtering for the AC signal goint to IC11 - this could reduce some effect of a poor mains waveform.

The supply decoupling can be critical at a few points: The PLL chip and IC11 - jitter here can cause noise and a frequency modulation from the input signal may cause INL errors.
The switches at IC6 may also be critical with the supply. At least they are possible sources of interference / noise. So it may be good to have more than just a decoupling cap, but also some series ferrite / resistor to separate it from the main supply.

The LTC1150 AZ (IC1) is an old and rather noisy type. The input impedance is rather high, so a very low noise type like OPA189 is not a good choice, but a AD8628 should be OK. There is no need to have a high supply for this OP: +- 2 V would be enough.
Ideally one could add a slope amplifier before the comparators - this may be lower noise than the LM311.

[rigrunner]

R6 and R20 in my diagram appear to be correct.

There are no top side traces for either R6 or R20 footprint, and R20 routes through a via to IC3  pin 3

IC1 and IC2 don't have any feedback other than C6 and C7

[rigrunner]

If one would really respin a PCB for the ADC here are a few points to consider:

Thanks for that. I'll tidy up the schematic and  apply your suggestions.

The decoupling of the supply is shockingly bad on the original PCB. There are a few 100nF scattered about the board, not necessarily near to IC supply pins.

Do you have an understanding of what IC7 is achieving? Half of it isn't connected and the other half is in a static state that doesn't seem to have a purpose. Other than shifting the references a little, removing it has no effect on operation.

[rigrunner]

Pictures of the ADC board

Originally the integrator side was potted 



It took a while but I eventually got the potting compound off - revealing

[branadic]

Thanks for sharing the pictures. The implementation of the reference is amazing, allthough I'm missing in copper etched excommunication to complete the magic. 

-branadic-

[Kleinstein]

The connection to ground via IC7 should have some purpose:  it avoids the point between IC6A and IC6B to be floating in the short time between the 2 phases with positive and negative reference. The controls by 2 switches in series is odd, but could still work. I would have more favored a logic connection and only 1 switch.  It should not be static.

The effect of removing this chip could be small, but effecting the INL. A few ppm change of the signal may not be much but could still be quite some effect on the INL.

The UART part at the 50 Hz clock input looks odd. It can still make sense to have the option to choose between an crystal clock and the 50 Hz mains signal. Though just connecting the 2 signals is kind of a fail  .


Decoupling is a tricky part. In many areas one can get away with surprisingly little. In other cases decopling can make quite some difference. It is a bit hard to tell upfront.  With my ADC version I see a measurable effect on how decouling near the oscillator is done. Other parts look possibly sensitive, but in my case did not show much effect. HP did notice an effect of decoupling capacitance at the integrator at the 3458 (though a different circuit). The relatively slow modulaton (200 Hz forcing frequency compared to some 330 kHz in the 3458 or 34401 can make some effects like decoupling and also clock jitter less important.
Still it makes not much sense to save on the decoupling - it is like 1 cent for a cap or resistor and maybe 5 cents for a ferrite.
From the pictures decoupling does not look so bad, though it could be better.

The part around R20 / R6 looks indeed suspect, but the pictures also look like that is the way it is.  Is the ouput of IC 3 at all active in this confuguration - this could explain why IC7 is also static, not doing much. The logic way would be 2 trigger levels just a bit separated, like +-10 mV from ground.

For the resistors at the ADC input one could also consider an resistor array and maybe get away with 150 K (instead of 160 K) and 100 K. It could be at least an alternative footprint. The input range would be a bit smaller.

[rigrunner]

The connection to ground via IC7 should have some purpose:  it avoids the point between IC6A and IC6B to be floating in the short time between the 2 phases with positive and negative reference. The controls by 2 switches in series is odd, but could still work. I would have more favored a logic connection and only 1 switch.  It should not be static.

The max313 IC7 switches are normally open. When powered on switch A closes, but switch D always stays open with the -10V applied to its control line.
The ground on IC7 pin 14 isn't utilised.

The effect of removing this chip could be small, but effecting the INL. A few ppm change of the signal may not be much but could still be quite some effect on the INL.

The UART part at the 50 Hz clock input looks odd. It can still make sense to have the option to choose between an crystal clock and the 50 Hz mains signal. Though just connecting the 2 signals is kind of a fail  .

It's a bizarre choice to have the UART enabled and have the pin as an input at the same time.

Decoupling is a tricky part. In many areas one can get away with surprisingly little. In other cases decopling can make quite some difference. It is a bit hard to tell upfront.  With my ADC version I see a measurable effect on how decouling near the oscillator is done. Other parts look possibly sensitive, but in my case did not show much effect. HP did notice an effect of decoupling capacitance at the integrator at the 3458 (though a different circuit). The relatively slow modulaton (200 Hz forcing frequency compared to some 330 kHz in the 3458 or 34401 can make some effects like decoupling and also clock jitter less important.
Still it makes not much sense to save on the decoupling - it is like 1 cent for a cap or resistor and maybe 5 cents for a ferrite.
From the pictures decoupling does not look so bad, though it could be better.

For the respin I'll add more decoupling closer to each IC. I'll re-route the supplies to. The clock generator and its subsequent dividers will get their own clean supply.

The part around R20 / R6 looks indeed suspect, but the pictures also look like that is the way it is.  Is the ouput of IC 3 at all active in this confuguration - this could explain why IC7 is also static, not doing much. The logic way would be 2 trigger levels just a bit separated, like +-10 mV from ground.

Screen grabs attached from pin 7 outputs of IC3 & 4. Taken with 10V input to the ADC board.

For the resistors at the ADC input one could also consider an resistor array and maybe get away with 150 K (instead of 160 K) and 100 K. It could be at least an alternative footprint. The input range would be a bit smaller.

Input resistors must be as low TCR as possible.  It's just about usable with a 3ppm/C, anything worse than that shows large drift with case temperature.

[TiN]

Cool looking, but pointless LTZ design . Also that wirelessly connected resistor near LT1013 opamp looks like just what needed for ultimate LTZ trim. 

What is the board with shield, "10 ohm" transformer and SMB connectors? AC board? I think the more photos shared the better, in case somebody in future wants to compare/repair different 8081s. You can upload RAW images to my FTP, I'll move them to 8081 folder.

[rigrunner]

The 390K is lifted because I was experimenting with trimming 

The board with the 10 ohm writing is the electrometer. That is also broken  I haven't bothered looking at repairing that board yet. No point until the rest of the DMM is working.

I've roughly scribbled the main functions on to the pictures you have on your site. Hopefully it will help if you're looking for a particular section?

[rigrunner]

The connection to ground via IC7 should have some purpose:  it avoids the point between IC6A and IC6B to be floating in the short time between the 2 phases with positive and negative reference. The controls by 2 switches in series is odd, but could still work. I would have more favored a logic connection and only 1 switch.  It should not be static.

The max313 IC7 switches are normally open. When powered on switch A closes, but switch D always stays open with the -10V applied to its control line.
The ground on IC7 pin 14 isn't utilised.

Looking at the Solartron 7081 schematic I see what is supposed to happen with IC7. In the 8081 it's broken by design 
I should be able to implement a fix that will short R10 to 0V in the dead time between IC6A and IC6B activity.

Modified like this

[Kleinstein]

For the resistors at the input the requitement is a low relative TC. This can be achieved with good resistors as shown, but also with a resistor array. The relative TC specs for LT5400 and MORN  arrays are quite good. In my ADC circuit I see a relative TC of around 1 ppm/K for ORN and NOMCA (not good noise wise) resistor arrays.  So the relative TC could be at an acceptable level. It may still need some tests. There is also the problem that LT5400 and MORN are quite small size and thus possibly more self heating.   With some luck the relative TC for the resistor array may be comparable to the BMF resistors. The advantage would be mainly a lower price and possibly faster (may be of the shelf) delivery.

There is anyway some residual TC from the switch resistance. With low R resistors and relatively large resistors at the input the effect would not be very large though. 12 Ohms / 100 K * 6000 ppm/K is 0.7 ppm/K contribution. So one may consider a possible compensation with a resistor of known positive TC in series to the input path. Something like a PT100 with some 100 Ohms in parallel could be an option for the compensation and may also be used for a little trim (only workung for the amplifier gain, but not the INL from self heating).

The comparator IC 3 seem to still work despite the odd resistor R20.

Thanks for the pictures with shown functions. I would guess the still unlabled part above the AC part should be the AC amplifier / rang switching.

The DC input part seems to also include an amplifier, not just a buffer. 

[rigrunner]

For the resistors at the input the requitement is a low relative TC. This can be achieved with good resistors as shown, but also with a resistor array. The relative TC specs for LT5400 and MORN  arrays are quite good. In my ADC circuit I see a relative TC of around 1 ppm/K for ORN and NOMCA (not good noise wise) resistor arrays.  So the relative TC could be at an acceptable level. It may still need some tests. There is also the problem that LT5400 and MORN are quite small size and thus possibly more self heating.   With some luck the relative TC for the resistor array may be comparable to the BMF resistors. The advantage would be mainly a lower price and possibly faster (may be of the shelf) delivery.

I'm thinking of putting footprints in for PWW and arrays along with the BMF. There will be plenty of space and as you mention, much cheaper.

There is anyway some residual TC from the switch resistance. With low R resistors and relatively large resistors at the input the effect would not be very large though. 12 Ohms / 100 K * 6000 ppm/K is 0.7 ppm/K contribution. So one may consider a possible compensation with a resistor of known positive TC in series to the input path. Something like a PT100 with some 100 Ohms in parallel could be an option for the compensation and may also be used for a little trim (only workung for the amplifier gain, but not the INL from self heating).

I'll bear this in mind.

The comparator IC 3 seem to still work despite the odd resistor R20.

If I tie pin 3 of IC3 to ground (as the Solartron does) the output from IC3 inverts but everything still works.

Thanks for the pictures with shown functions. I would guess the still unlabled part above the AC part should be the AC amplifier / rang switching.

The DC input part seems to also include an amplifier, not just a buffer. 

You are quite right on both accounts. I quickly scribbled on Tin's pictures without much thought for finite detail.
I'll try to take some pictures of all of the sections and make a better attempt at showing each one.

[Kleinstein]

If I tie pin 3 of IC3 to ground (as the Solartron does) the output from IC3 inverts but everything still works.

I don't think the signal would really be inverted, it is more like a change in the signal that makes it looks like it. With 3 possible states of positive zero and negative reference there are more options to get the same feedback. The change in the comparator level would change from zero to positive/negative combinations. It may also effect the maximum range for the signal. It depends one the details of the forcing signal how large the range is. AFAIK the useful range is largest with quite some difference between the comparator levels.

I am a bit surprised that the clock frequency is quite low with only 6.25 MHz for the synchronizing flip-flops. This would limit the resolution at  short (e.g. less than 10 seconds or so) integration time. The newer Solartron DMMs use a really high clock frequency (close to 50 MHz).

A point to consider would be to change the option to choose a crystal based clock instead of the 50 Hz PLL. The old, likely not working way with the UART signal would still have the jitter from the PLL. The better way would be to switch the clock behind the PLL chip, so that the crystal clock would be low jitter.
I have looked at the noise for a multi-slope and similar ADC quite a bit. So I could do an analysis of the expected noise levels and the expected dominant noise sources. What are the relevant integration times used ? I would expect them to use mainly longer integration, like 10 seconds. I would expect the performance for short integration quite poor and quantization limited.

[rigrunner]

I am a bit surprised that the clock frequency is quite low with only 6.25 MHz for the synchronizing flip-flops. This would limit the resolution at  short (e.g. less than 10 seconds or so) integration time. The newer Solartron DMMs use a really high clock frequency (close to 50 MHz).

A point to consider would be to change the option to choose a crystal based clock instead of the 50 Hz PLL. The old, likely not working way with the UART signal would still have the jitter from the PLL. The better way would be to switch the clock behind the PLL chip, so that the crystal clock would be low jitter.

One of the use cases for the CS2000 pll is jitter removal. I guess they chose it for this reason?

I have looked at the noise for a multi-slope and similar ADC quite a bit. So I could do an analysis of the expected noise levels and the expected dominant noise sources. What are the relevant integration times used ? I would expect them to use mainly longer integration, like 10 seconds. I would expect the performance for short integration quite poor and quantization limited.

The fastest integration time with 8 digits is 4 seconds. Maximum selectable is 64 seconds.
Fastest at 7 digits is 1 second, and at 6 digits or less fastest is 125ms.

In 8 digit mode at 4 second integration the last digit appears to be restricted to increments of 6 or 7. e.g. 10.000,000,0V would move to either 10.000,000,6 or 9.999,999,3 - is this your expected quantization limit in action?

[Kleinstein]

The 0.6 to 0.7 µV steps after 4 seconds corresponds to the simple calculation:
With 160K and 100 K at the ADC the theoretical range would be up to 16 V. This is divided by 6.25 MHz  and 4 seconds which results in some 0.64 µV steps.

In theory there may be a little extra resolution from looking at more start / stop values (a bit like higher order filter), but it seem to be not using this and the rather slow (200 Hz) modulation does not make this very attractive.

I would normally call this 7 bit resolution, not much better.
Similar I don't think 125 ms would really give 6 digits. I should more like takes 250 ms for digits.
Theoretical  ( use the root of 12 factor) 0.64 µV quantization would correspond to 180 nV RMS noise - if this would be simple quantization with no other noise. However here it is quantization at the start and stop at least, so 250 nV expected quantization noise alone after 4 seconds. So some 10 seconds integration to get 100 nV quantization noise (still more than 100 nV steps !).

The CS2000 may be used for jitter removal for the 50 Hz mains clock, but the jitter specs I found (~60 ps) are not that great compared to a low cost crystal oscillator (e.g. 1 ps range). Jitter specs are still a bit tricky, as there are different conditions / time windows used. There would be additional jitter from the logic anyway, but better than 10 ps jitter would be nice for the clock. It may be a good PLL, but even with a very good input signal it is hard to get good jitter specs for the much higher clock. The importance of jitter scales with the square root of the modulation frequency. So jitter is much less (e.g. a factor of 30) important than with the fast modulation MS-ADCs. So the PLL may be just good enough to be not a mayor problem.  Chances are the rather slow modulation is chosen because of jitter from the PLL.
The effective input noise from jitter should be square root of the switching frequency (4x200 Hz) times the jitter amplitude, times 16 V (theoretical range). So this would be some 27 nV/sqrt(Hz) and thus still OK. a poor mains signal may still add jitter, though the PLL (seems to be digital) could be quite good in suppression here and may not add much extra noise.

An easy to handle noise source are the resistors at the integrator. As the noise adds as current noise the 100 K would act like about 256 Kohms in series to the input. So a total effective resistance of 416 Kohms or some 83 nV/sqrt(Hz) from the resistor Johnson noise alone.

The OPs (LTC1150) low frequency noise is multiplied by a factor of 2.6 4.16 due to the resistor ratio. So this would be some 350 nV/sqrt(Hz) 220 nV/sqrt(Hz)- a major noise source. So it could be worth using a lower noise OP here. They are available, with more choice with a low supply voltage, which would be sufficient.

The overall input referred noise sources should be at some  400 300 nV/sqrt(Hz). For 4 s integration the BW is 1/8 Hz. So the white noise would correspond to some  140 100 nV_rms. So at 4 seconds the quantization noise may still be dominant to the other noise sources. Less noise from the OP would mainly be effective a longer integration, like 16 seconds or more.

The higher frequency noise of the OP27 and the LM311 comparators would compete with the quantization noise as they have the same dependence on the integration time.
It is a bit hard to estimate an effective BW and noise for the LM311. The bias current suggest a noise level in the 10 nV/sqrt(Hz) range. For the BW I would estimate some 10 MHz, maybe a little more.
This would give a high frequency RMS noise of some 30 µV. The slope is  10 V / 100K / 100 nF = 1 V/ms.
So the 30 µV would correspond to 30 ns_rms for the comparator timing. With 6.25 MHz the quantization noise is at some 46 ns_rms  and thus comparable. Reducing the comparator noise would thus be only partially effective, as there is still the limited quantization.

So for 4 second integration I would expect the main noise sources to be
1) quantization: ~ 180 nV_RMS
2) LM311        ~  120 nV_RMS
3) LTC1151     ~  125 80 nV_RMS

The LTC1151 noise gets more important for longer integration, less for shorter integration.

For a board remake, the question is, if this is meant only to be used in the transmille DMM or possibly also "standalone" with maybe a simple extra front end (e.g. buffer only).

[rigrunner]

There are a quite a few things there to take into consideration. I'll need to digest and ponder a little.

For a board remake, the question is, if this is meant only to be used in the transmille DMM or possibly also "standalone" with maybe a simple extra front end (e.g. buffer only).

A stand-alone PCB isn't something I'd considered...
If I do place the reference on the ADC board it lends itself even more to becoming a stand-alone option. Yes, OK I'm game 
If the remake PCB for the DMM works i'll take that as the base and if you're willing to assist in upgrading I'll turn that into a stand-alone that others can make too.

I have the firmware from the two PIC micros that can also be reworked if needs be, but that might require someone with good PIC skills to make that happen quickly.

[Kleinstein]

Even with some slight improvements (e.g. 2x the clock, lower noise OP, slope amplifier to improve on LM311 noise) the performance of the ADC is still not great. The INL may be good, but there are enough details to do wrong here.

For a standalone version a simple LM399 reference may be good enough. It still needs the +-10 V scaling part, which can be one of the most critical parts from the components. An error in the ratio of 10 V to -10 V would result in an offset error / noise to the ADC. So the OPA177 used there could be a major noise and drift source, if there is no extra auto zero mode (which is a bit tricky with the slow ADC).