Transmille 8081 ADC

[rigrunner]

The CS2000 may be used for jitter removal for the 50 Hz mains clock, but the jitter specs I found (~60 ps) are not that great compared to a low cost crystal oscillator (e.g. 1 ps range). Jitter specs are still a bit tricky, as there are different conditions / time windows used. There would be additional jitter from the logic anyway, but better than 10 ps jitter would be nice for the clock. It may be a good PLL, but even with a very good input signal it is hard to get good jitter specs for the much higher clock. The importance of jitter scales with the square root of the modulation frequency. So jitter is much less (e.g. a factor of 30) important than with the fast modulation MS-ADCs. So the PLL may be just good enough to be not a mayor problem.  Chances are the rather slow modulation is chosen because of jitter from the PLL.
The effective input noise from jitter should be square root of the switching frequency (4x200 Hz) times the jitter amplitude, times 16 V (theoretical range). So this would be some 27 nV/sqrt(Hz) and thus still OK. a poor mains signal may still add jitter, though the PLL (seems to be digital) could be quite good in suppression here and may not add much extra noise.

It would be simple enough to reconfigure the 74HC390 chain to divide down the new 10MHz oscilator to 200Hz and remove the whole 50Hz line sync and pll. Would anything be lost by doing this? I'm thinking perhaps mains frequency immunity might be a side effect of syncing to it?

The OPs (LTC1150) low frequency noise is multiplied by a factor of 2.6 4.16 due to the resistor ratio. So this would be some 350 nV/sqrt(Hz) 220 nV/sqrt(Hz)- a major noise source. So it could be worth using a lower noise OP here. They are available, with more choice with a low supply voltage, which would be sufficient.

I've added your earlier suggestion of the AD8628 to my updated schematic. With a pair of 13V zeners from the 15V rails to run it at +/-2V. The 5V rails are noisy and full of hash.

So for 4 second integration I would expect the main noise sources to be
1) quantization: ~ 180 nV_RMS
2) LM311        ~  120 nV_RMS
3) LTC1151     ~  125 80 nV_RMS

For

1) it would need the modulation probably quadrupling and the software tweaking to make any real reduction.
2) does switching to an LT1011 help here? 20-25nA IB.
3) this is the low hanging fruit. Do this first and tweak other stuff afterwards.

For a standalone version a simple LM399 reference may be good enough. It still needs the +-10 V scaling part, which can be one of the most critical parts from the components. An error in the ratio of 10 V to -10 V would result in an offset error / noise to the ADC. So the OPA177 used there could be a major noise and drift source, if there is no extra auto zero mode (which is a bit tricky with the slow ADC).

I've previously wondered if an LT1044A might be put into use to generate the -10V. Or something similar to how Datron 12x1 generate their inverted reference. Leaving only the 7->10V boost amp and one divider as main noise and drift sources.

[TiN]

I did run few INL tests for 8081. Setup is typical, source was calibrated Fluke 5720A.
For completeness and sanity check other DMMs also connected in parallel.

HP3485A is old good unit
HP3458B is Agilent unit with drifty A3 ADC
K2182 was used with channel 1
F8508A is RESL8. FILT_OFF mode

All units were configured same NPLC30 readout, guard floating.

[Kleinstein]

For improving on the quatization noise, it would be a faster clock for measuring the timing. Usually the signal from one of the comparators is used (here by the PIC) to measure the exact timing at the start and end of conversion. A faster clock would likely need a modified software, except maybe a simple factor of 2 for all and than getting half the integration time than set. The crazy case would be to also directly measure the time at the comparator output with some time to digital solution. There are ways to convert the time difference at HC175 flipflop to an analog voltage, as a kind of analog interpolator. Similar solutions are used in high resolution counters / timers. It may not even need that much extra HW, but quite some addition to the software.

For the comparator noise the bias current gives an indirect hint on the current used in the input stage and this way the noise. So a higher bias is more like indicating low noise. The way to reduce the noise would be a kind of slope amplifier (only needed for one of the comparators,but could be used for both). This would be an extra low noise (e.g. OP27, NE5534) OP adding gain (e.g. 5 x) and limiting the bandwidth (no need to be super fast like the comparator, some 0.5 to 2 MHz BW should be enough).
The noisy part in a slope amplifier may be actually a resistor and for the extremes one would use JFETs there, like in some very old meters.
Something like a factor of 2-3 comparator noise reduction should be easy from the reduced BW. Maybe another factor 1.5 from lower noise from lower amplifier noise, though in the simple form a 6 K resistor may have similar noise as the LM311. Just an RC filter would not work, as much of the noise is likely from the comparator itself.

Speeding up the modulation could help indirectly: with a faster modulation the integration capacitor could be smaller and thus less charge noise from the same voltage noise. However faster modulation makes the jitter and possible switching artifacts more important. The PIC software would also have slightly less time, though likely not so critical.
A slight change in the modulation speed (e.g. 250 or 300 Hz) would be probably still acceptable, but it should still be an multiple of 50 Hz.

The mains syncronous PLL has some sense. The mains suppression is quite a bit better in synchronous mode. With a relatively high hum level there can be additional problems to the normal residual beat frequency. However with a poor mains waveform the PLL could also be major noise source. I don't know how good the PLL is in removing jitter from the mains input. Not all jitter parts are equally bad and it is thus hard to judge. So it would be nice to have both options: with a mains PLL or with a stable low jitter crystal clock. It depends on the conditions which mode works best. Some of the Solartron meters (AFAIR the 7061) have the option for a crystal clock instead of the PLL, though AFAIK no easy switching between the 2 options.

For the supply of the low voltage AZ OP, I would not use simple series Zeners to reduce the voltage. More like extra filtering and than zeners, LEDs  (or TL431) as shunt regulators. With enough filtering even noisy +-5 V may not be so bad.

A switched capacitor part for the -10 V generation would definitely be a possible way. It still needs some fitlering for the output. The amplifier for the -10 V part would also add to the noise. If the original is an OPA177 one would see it's low frequency part, so possibly quite some 1/f noise.  Similar noisy resistors (like an NOMCA array) could add quite some 1/f noise.

I would expect the meter to use only very infrequent drift correction like the Solartron meters.  So the effective frequency is very low.


The INL does not look very good. With a noisy supply this is not such a surprise, though the square law part does not look that much like supply coupling. Maybe more loading down the references.

[rigrunner]

For improving on the quatization noise, it would be a faster clock for measuring the timing. Usually the signal from one of the comparators is used (here by the PIC) to measure the exact timing at the start and end of conversion. A faster clock would likely need a modified software, except maybe a simple factor of 2 for all and than getting half the integration time than set. The crazy case would be to also directly measure the time at the comparator output with some time to digital solution. There are ways to convert the time difference at HC175 flipflop to an analog voltage, as a kind of analog interpolator. Similar solutions are used in high resolution counters / timers. It may not even need that much extra HW, but quite some addition to the software.

I may tackle this after the other changes are in place. Even though the code in each PIC is small it will take me some time to disassemble and comment it.

For the comparator noise the bias current gives an indirect hint on the current used in the input stage and this way the noise. So a higher bias is more like indicating low noise. The way to reduce the noise would be a kind of slope amplifier (only needed for one of the comparators,but could be used for both). This would be an extra low noise (e.g. OP27, NE5534) OP adding gain (e.g. 5 x) and limiting the bandwidth (no need to be super fast like the comparator, some 0.5 to 2 MHz BW should be enough).
The noisy part in a slope amplifier may be actually a resistor and for the extremes one would use JFETs there, like in some very old meters.
Something like a factor of 2-3 comparator noise reduction should be easy from the reduced BW. Maybe another factor 1.5 from lower noise from lower amplifier noise, though in the simple form a 6 K resistor may have similar noise as the LM311. Just an RC filter would not work, as much of the noise is likely from the comparator itself.

Would this be acceptable to place between the output of IC2 and inputs to both comparators? Would lower value resistors than the 1K/4K3 lower the noise further?



(inline image doesn't seem to be working for me  )

Speeding up the modulation could help indirectly: with a faster modulation the integration capacitor could be smaller and thus less charge noise from the same voltage noise. However faster modulation makes the jitter and possible switching artifacts more important. The PIC software would also have slightly less time, though likely not so critical.
A slight change in the modulation speed (e.g. 250 or 300 Hz) would be probably still acceptable, but it should still be an multiple of 50 Hz.

The mains syncronous PLL has some sense. The mains suppression is quite a bit better in synchronous mode. With a relatively high hum level there can be additional problems to the normal residual beat frequency. However with a poor mains waveform the PLL could also be major noise source. I don't know how good the PLL is in removing jitter from the mains input. Not all jitter parts are equally bad and it is thus hard to judge. So it would be nice to have both options: with a mains PLL or with a stable low jitter crystal clock. It depends on the conditions which mode works best. Some of the Solartron meters (AFAIR the 7061) have the option for a crystal clock instead of the PLL, though AFAIK no easy switching between the 2 options.

I have replaced the 47K resistor in the mains sampling input with a low pass.
I can get a 6.25MHz oscillator from mouser, there should be enough room to have it alongside - or perhaps add another chain of HC390 to divide the 10MHz micro clock to 200Hz with a solder bridge select. Tying the PLL lock detect low allows start up to continue with the PLL disabled.

For the supply of the low voltage AZ OP, I would not use simple series Zeners to reduce the voltage. More like extra filtering and than zeners, LEDs  (or TL431) as shunt regulators. With enough filtering even noisy +-5 V may not be so bad.

I'll play around with the supply options...

A switched capacitor part for the -10 V generation would definitely be a possible way. It still needs some fitlering for the output. The amplifier for the -10 V part would also add to the noise. If the original is an OPA177 one would see it's low frequency part, so possibly quite some 1/f noise.  Similar noisy resistors (like an NOMCA array) could add quite some 1/f noise.

Y1365V0008QT or LT5400AHMS8E-1 both look OK TCR wise. Would they be OK noise wise?
Vishay part is twice the cost of the LT.

I would expect the meter to use only very infrequent drift correction like the Solartron meters.  So the effective frequency is very low.


The INL does not look very good. With a noisy supply this is not such a surprise, though the square law part does not look that much like supply coupling. Maybe more loading down the references.

The UART signal being pulled to ground was causing lots of 50Hz noise on the +5V rail, and the logic inputs of a MAX313 were connected to the +/-10V references. Would they have an effect on INL?

@TiN It will be interesting to compare the modified 8081 to the set you checked out. I only have an un-calibrated 5440B to run against.

Edit: Typo on low pass R18 and R24 should read 24K.

[Kleinstein]

The slope-amplifier usually has additional back to back diodes in the feedback, so the OP is not driven so hard into saturation and also the comparator sees only a smaller signal.  In addition a cap to reduce the BW may be good. A single slope amplifier for both comparators can be OK if the 2 trigger levels are similar (e.g. within some 400 mV after the gain). The less critical comparator could also use to signal directly from the integrator - usually only one comparator is used for the start / stop of integration, though in theory both could be used with averaging for reduced noise.

The resistor values are a balance between the noise and the current drawn: there could be quite a bit of current with a large input from the integrator.
I don't think it is needed here, as the quatization noise is more limiting, but as an alternative solutuion one could replace the low resistor with 2 JFETs, to give a low resistance at low current and than limit the current to some 1-3 mA. The exact gain of the amplifier is not critical, only that it is reasonable stable for one convesion. I would consider the main advantage in a reduced (controllable) bandwidth, not so much in having a lower noise density to start with.

With reusing the µC code in a new board there could be a copy-right problem. So there could be a catch with the stand-alone idea. 
Ideally it would be a new software and just get the info on the interfaces / messages. Still not sure if this would worth the effort. The ADC is still not very low noise, slow (or limited resolution)  and quite some effort. I may be a bit biased here, as I have my own ADC design with less effort and noise. However it is made for an AZ mode in the front end and thus not easy to use in the 8081 environment.

The jitter is slightly less critical with the 200 Hz forcing signal, than with the clock to the HC175 flip-flops. If the 10 MHz µC clock would be used, one could also use a µC timer to create the 200 (or 400 Hz) signal - so no need for another divider chain, just switching of the clocks.
As far as I see it the CS2000 should normally run with 3.3 V supply - though 5 V supply is still in the absolute maximum range.  Lower supply would reduce the supply current and spikes. Not many parts actually need the full 5 V (e.g. the RS232 and external control).

The LT5400 resistor array should be OK from the noise. Normally the higher tolerance version should be OK too. It is not so impoartant that the 2 are really accurate, but they should be very stable over the time of a experiment (e.g. a few hours). Drift of the resistors results in offset drift of the ADC. 1ppm ratio dirft would correspond to some 16 µV ADC drift. So there is a reason one wants resistor excess noise levels very low (e.g. better -50 dBi).
Noise of the amplifier for the inversion comes to the result with a gain of 1.6  (or whatever the resistor ratio at the integrator).

The capacitor C1 looks quite large to me. I think one should get away (and get a better settling after jumps) with a little less capacitance. I see no real need for a PP cap here. A smaller size MKS type should be sufficient. Similar C2 should be OK with MKS and less size to reduce the parasitic capacitance.

The max313 not switching correctly and thus a floating resistor could be an INL issue, though this is hard to tell. If the 2 compararator levels are close togehter, the high Z phase would be only quite short and not too variable in length. Some 50 Hz hum on the 5 V supply would be less of an issue, but if the state or switching of the HC175 or the 200 Hz signal has an effect on the 5 V supply and this effects the 10 MHz clock at the CS2000, this could be an issue.

My main suspect for the square law INL part is an effect of the charge injection of the max312 switches to the +-10 V reference signals. With rather large 3.3 µF caps, the recovery of the reference signal can take quite some time. So while the large caps help to keep the spikes small, they also extend the time. It may be worth testing smaller caps there, so that the reference signal would recover in less than some 100 µs. Short pulses would more like cause an offset only, not INL.  INL is possible if the recovery takes longer than to the next time the reference is switched.  It may be good to have seprate buffers for the forcing signal and the main reference signals to the other half of the max312.  The extra buffers are quite some effort.

For linearity testing calibration of the 5440 calibrator should not be very important.

[rigrunner]

The slope-amplifier usually has additional back to back diodes in the feedback, so the OP is not driven so hard into saturation and also the comparator sees only a smaller signal.  In addition a cap to reduce the BW may be good. A single slope amplifier for both comparators can be OK if the 2 trigger levels are similar (e.g. within some 400 mV after the gain). The less critical comparator could also use to signal directly from the integrator - usually only one comparator is used for the start / stop of integration, though in theory both could be used with averaging for reduced noise.

This is my current iteration. The GBW of the OP27 is 8MHz. Gain setting is x174 that gives a BW of 45KHz. Too tight?

The resistor values are a balance between the noise and the current drawn: there could be quite a bit of current with a large input from the integrator.
I don't think it is needed here, as the quatization noise is more limiting, but as an alternative solutuion one could replace the low resistor with 2 JFETs, to give a low resistance at low current and than limit the current to some 1-3 mA. The exact gain of the amplifier is not critical, only that it is reasonable stable for one convesion. I would consider the main advantage in a reduced (controllable) bandwidth, not so much in having a lower noise density to start with.

I've changed them to reduce current, increase gain and the anti parallel diodes should prevent saturation. The low resistor is a small value now, so shouldn't require JFETs.

With reusing the µC code in a new board there could be a copy-right problem. So there could be a catch with the stand-alone idea. 
Ideally it would be a new software and just get the info on the interfaces / messages. Still not sure if this would worth the effort. The ADC is still not very low noise, slow (or limited resolution)  and quite some effort. I may be a bit biased here, as I have my own ADC design with less effort and noise. However it is made for an AZ mode in the front end and thus not easy to use in the 8081 environment.

A fair comment regarding copyright. When I take a look at tweaking the software I'll have an idea of what is involved and how tricky new software will be.

The jitter is slightly less critical with the 200 Hz forcing signal, than with the clock to the HC175 flip-flops. If the 10 MHz µC clock would be used, one could also use a µC timer to create the 200 (or 400 Hz) signal - so no need for another divider chain, just switching of the clocks.

Good point. I'll take a look at that.

As far as I see it the CS2000 should normally run with 3.3 V supply - though 5 V supply is still in the absolute maximum range.  Lower supply would reduce the supply current and spikes. Not many parts actually need the full 5 V (e.g. the RS232 and external control).

Lowering the supply to the CS2000 would further isolate it from the other supplies and noise. I can experiment with this on the current board prior to the rework.

The LT5400 resistor array should be OK from the noise. Normally the higher tolerance version should be OK too. It is not so impoartant that the 2 are really accurate, but they should be very stable over the time of a experiment (e.g. a few hours). Drift of the resistors results in offset drift of the ADC. 1ppm ratio dirft would correspond to some 16 µV ADC drift. So there is a reason one wants resistor excess noise levels very low (e.g. better -50 dBi).
Noise of the amplifier for the inversion comes to the result with a gain of 1.6  (or whatever the resistor ratio at the integrator).

I'll add a footprint for the LT5400, along with PWW and VHP.

The capacitor C1 looks quite large to me. I think one should get away (and get a better settling after jumps) with a little less capacitance. I see no real need for a PP cap here. A smaller size MKS type should be sufficient. Similar C2 should be OK with MKS and less size to reduce the parasitic capacitance.

I'll test some other values and types on the existing board and see what difference it makes. I think I have some 220nF mkp caps hanging around.

The max313 not switching correctly and thus a floating resistor could be an INL issue, though this is hard to tell. If the 2 compararator levels are close togehter, the high Z phase would be only quite short and not too variable in length. Some 50 Hz hum on the 5 V supply would be less of an issue, but if the state or switching of the HC175 or the 200 Hz signal has an effect on the 5 V supply and this effects the 10 MHz clock at the CS2000, this could be an issue.

The 5V rail has a small amount of 200Hz + 50Hz remaining on it. More bulk and bypass caps to be added and maybe some ferrites for the clock part.

My main suspect for the square law INL part is an effect of the charge injection of the max312 switches to the +-10 V reference signals. With rather large 3.3 µF caps, the recovery of the reference signal can take quite some time. So while the large caps help to keep the spikes small, they also extend the time. It may be worth testing smaller caps there, so that the reference signal would recover in less than some 100 µs. Short pulses would more like cause an offset only, not INL.  INL is possible if the recovery takes longer than to the next time the reference is switched.  It may be good to have seprate buffers for the forcing signal and the main reference signals to the other half of the max312.  The extra buffers are quite some effort.

This is a deviation from the 7081. Are the 3u3 caps there because the reference is 30cm away?
I have some similar 1uF caps that I can try in place.

Edit: Forgot to add that the REFBUF signals are buffered from the OP177 REF signals by OP27. These are also 30cm away from the ADC PCB.

For linearity testing calibration of the 5440 calibrator should not be very important.

[Kleinstein]

At the slope amplifier the resistor to ground would still see nearly the full input voltage (integrator swing). This is why one can not use a really small resistor there. I would consider some 2 K the practical minimum. If really less noise is needed, 2 JFETs (low threshold) with a resistor in between would be the option to get low resistance in the critical range and still limit the current.

I think 140 x gain would be a bit too much and too slow. The minimum pulse length should be around 100 µs and settling should be quite a bit faster. So I would like to have still some 100 kHz BW at least. There is also no real need to lower this noise part that much: the quatization noise is comparable, if not higher. So a factor 10 down in the BW and thus a factor of 3 in the noise should be enough.This would still allow some 5 K as the lower resistor.
Anyway it is only a question of resistor value, not effecting the layout.

For the value of C1 and the spacing of the compartors it may make sense to run a simulation (e.g. LTspice). The value effect the speed a stable integrator waveforme is reached and thus the settling time are a jump. Not well settled the INL error can be larger, depeding on how much math is used for the result.

I think the 2.2 µF (or 3.3 ?) caps at the reference are there to reduce the drop in the voltage from the charge injection. The long trance may be part of the reason, though there is still a limited speed of the buffer. The reference for the forcing signal would be the slightly less critical part.
One may be able to lower the capacitance quite a bit - like in the 100 nF maybe even 10 nF range. The buffers can be quite a critical part. Extra Buffers would also add noise and drift.

[rigrunner]

I think the 2.2 µF (or 3.3 ?) caps at the reference are there to reduce the drop in the voltage from the charge injection. The long trance may be part of the reason, though there is still a limited speed of the buffer. The reference for the forcing signal would be the slightly less critical part.
One may be able to lower the capacitance quite a bit - like in the 100 nF maybe even 10 nF range. The buffers can be quite a critical part. Extra Buffers would also add noise and drift.

Experimenting with values for the 3u3 capacitors turned up something unexpected.
With my IC7 modification removed and the circuit restored to original static state I can drop the capacitor values down to 100nF without any adverse effects.
With my IC7 modification in place the -10VREF, -10VREFBUF and 10VREFBUF are still fine down to 100nF, but the 10VREF goes into wild oscillation.
With 3u3 it is stable. With 1uF there is oscillation at mid 30s KHz and with 100nF oscillation is at mid 40s KHz.

Also noticed another deviation from the 7081 implementation. The forcing waveform on the 7081 appears to be 0V (both reference voltages switched together via 1K resistors) whereas the 8081 switches both references separately.

[Kleinstein]

The DG301 should be a SPDT switch. So the 1 K resistors at the Solartron 7081 are just at the reference side, reducing the switching spikes to the reference. So they effectively replace the buffers there.

A large capacitor like the 3.3 µF usually needs an amplifier / buffer that is made to tolerate this capacitance. If it oscillates with a slightly smaller cap (like 1 µF) this is not a good sign: it is likely not very stable with the 3.3 µF either.  If it is just an OP with no extra measures it would need something like a series resistor or manybe a capacitor and RC in parallel (e.g. 100 nF to ground and 22 Ohms + 220 nF  in parallel). Which combination is suitetable depends on the OP and details of the amplifier / buffer.

[rigrunner]

The DG301 should be a SPDT switch. So the 1 K resistors at the Solartron 7081 are just at the reference side, reducing the switching spikes to the reference. So they effectively replace the buffers there.

When the forcing waveform drive signal is applied the two references are combined to cancel out. The 8081 switches the forcing waveform between +ve and -ve reference.

A large capacitor like the 3.3 µF usually needs an amplifier / buffer that is made to tolerate this capacitance. If it oscillates with a slightly smaller cap (like 1 µF) this is not a good sign: it is likely not very stable with the 3.3 µF either.  If it is just an OP with no extra measures it would need something like a series resistor or manybe a capacitor and RC in parallel (e.g. 100 nF to ground and 22 Ohms + 220 nF  in parallel). Which combination is suitetable depends on the OP and details of the amplifier / buffer.

The 10V reference is an OP177 with a vishay 25K/10K divider to give 1.4x gain
Negative reference is another OP177 with the usual 10K/10K arrangement.
Both have 10nF MKS feedback capacitors and a 220pF cap across their respective inputs.

I'll experiment with them later to try and find out why one goes into oscillation but the other doesn't.

[Kleinstein]

The forcing signal needs to switch from +ref to -ref.  The DG301 has one of the 2 switches with inverted polarity. So the drawing is misleading and there is only one ref. active at a time (except maybe for a very short time, if there is no defined break before make).

The OPA177 probably does not like driving a hefty capacitive load. The 220 pF across the inputs may help, but this is probably still only borderline stable and slow settling. The usual circuit to drive a highly capacitive load is with an extra series resistor and seprate high and low frequency feedback. For fast settling one would include a fast in loop buffer and low ohms series resistor (e.g. 20 ohms range - what the buffer can compftably drive). Ideally the OP for the inverter would be lower low-frequency noise and maybe an AZ OP like LTC2057. For the 0.1 Hz noise the OPA177 is not that great.
 
The buffers with the less critical forcing signal are good: so spikes from the forcing signal would not effect the main reference, which would cause an INL error. A simple buffer would still be OK - it does not even have to be super stable, as the output is AC coupled anyway. So the OP27 there are more like overkill, but OK.  Filtering the signal to the buffers for the forcing signal would be nice and simple. It would avoid coupling the other way around, though this is allready less critical.

Extra buffers instead of the large filter caps could be an option, but the bufers would add noise and drift. So ideally it would be directly the 7 to +-10 V circuit that has good drive power, so it would get away with smaller caps (e.g. more like 10 or 100 nF and not 3 µF).

I had a though on the value of C1:  the large capacitance helps getting a known slope for the start to stop difference. A smaller cap would give more noise with a not so stable signal and thus waveform. So there is justification for the large cap. The option for a smaller cap at the forcing signal is with a slightly different, related ADC version that uses a separate "integrator" for the forcing signal.

[rigrunner]

The forcing signal needs to switch from +ref to -ref.  The DG301 has one of the 2 switches with inverted polarity. So the drawing is misleading and there is only one ref. active at a time (except maybe for a very short time, if there is no defined break before make).

That makes sense. The diagram looks to show both switches operating at the same time in parallel. 

The OPA177 probably does not like driving a hefty capacitive load. The 220 pF across the inputs may help, but this is probably still only borderline stable and slow settling. The usual circuit to drive a highly capacitive load is with an extra series resistor and seprate high and low frequency feedback. For fast settling one would include a fast in loop buffer and low ohms series resistor (e.g. 20 ohms range - what the buffer can compftably drive). Ideally the OP for the inverter would be lower low-frequency noise and maybe an AZ OP like LTC2057. For the 0.1 Hz noise the OPA177 is not that great.

As a test I powered the 8081 on with 100nF caps in place of the 3u3 and with the 220pF across the OP177 removed, and the oscillation frequency has almost halved. Resistor for the next test.

I'll add swapping the inverter to LT2057 to my notes. For tweaking later.



 

The buffers with the less critical forcing signal are good: so spikes from the forcing signal would not effect the main reference, which would cause an INL error. A simple buffer would still be OK - it does not even have to be super stable, as the output is AC coupled anyway. So the OP27 there are more like overkill, but OK.  Filtering the signal to the buffers for the forcing signal would be nice and simple. It would avoid coupling the other way around, though this is allready less critical.

Extra buffers instead of the large filter caps could be an option, but the bufers would add noise and drift. So ideally it would be directly the 7 to +-10 V circuit that has good drive power, so it would get away with smaller caps (e.g. more like 10 or 100 nF and not 3 µF).

If I can get rid of the oscillation I'll keep testing with lower caps. Would you keep the film caps as for the 3u3 replacements?

I had a though on the value of C1:  the large capacitance helps getting a known slope for the start to stop difference. A smaller cap would give more noise with a not so stable signal and thus waveform. So there is justification for the large cap. The option for a smaller cap at the forcing signal is with a slightly different, related ADC version that uses a separate "integrator" for the forcing signal.

Does the physical size of C1 & C2 have any benefit to the circuit?

[rigrunner]

There's something odd going on here that eludes me.

Original IC in 10V boost stage was OP177.

[ Specified attachment is not available ]

With ADC PCB unplugged and traces to the other two outputs cut so that the OP output is isolated it still oscillates.

Remove 220pF across inputs, still oscillates
Swapped OP177 with a new one, still oscillates.
Swapped vishay divider for pair of S102, still oscillates.
Swapped those for pair of PWW, still oscillates.
Swapped those for pair of S102 10K, perfectly stable.

Put divider back to 25K/10K and swapped OP177 for OPA277, oscillates again.
Replaced OPA277 with LT2057, still oscillates.

[ Specified attachment is not available ]

Adding the 3u3F between the OP and GND for any of the oscillating states and everything is stable.

 


Edit: added 10nF to circuit

[Kleinstein]

With the capacitive load from the ADC board most OPs will tend to oscillate.
Without the capacitive load the OPs should be stable. The type of resistors should not make a difference, especially not with already the 10 nF cap in the feedback.
The 2 OPs for the gain stage and the inverter may couple though the supply. Especially the negative supply has rather poor PSRR. The OPA177 is however not that fast to be really picky on the decoupling or prone to oscillation.

I somewhat doubt it can be so simple as putting the 220 pF cap between the inputs to make the OPA177 stable with a large ( > 10 nF) capacitive load. Even if stable it would be more like marginally stable and still not good: instead of a short drop there would be ringing. The amplitude may not be visible with the short spikes from the switches, but it could still cause trouble.

The OPA202 may be slightly more tolerant to capacitive load, but I doubt it would help with more then 100 nF.
They mention 25 nF with still a fast recovery. This is already quite good for a BJT based OP. For some reason I don't know good capacitive drive capability is more often found with FET based types

The Solatron circuit gets away without extra capacitors at the references output. So it may be still an option to totally skip on the 3.3 µF caps at the references (quite sure this is OK for the forcing signal with the extra buffers). For the main reference I would consider something like 50-100 ohms in series with some 10-100 nF as a little support, but without negative effect on the stability.

Small physical size of C1 and c2 could reduce parasitic capacitance and hum pic up, but is not that critical.

[rigrunner]

With the capacitive load from the ADC board most OPs will tend to oscillate.
Without the capacitive load the OPs should be stable. The type of resistors should not make a difference, especially not with already the 10 nF cap in the feedback.
The 2 OPs for the gain stage and the inverter may couple though the supply. Especially the negative supply has rather poor PSRR. The OPA177 is however not that fast to be really picky on the decoupling or prone to oscillation.

I expected the OP to be stable after isolating the output. I'm still scratching my head as to why it isn't. Stable at unity 2x gain with 2 x 10K but oscillating at 1.4x gain still makes no sense to me.

I have added extra decoupling at the supply rails and that makes a noticeable different to the supplies, but no change to the oscillation.

The Solatron circuit gets away without extra capacitors at the references output. So it may be still an option to totally skip on the 3.3 µF caps at the references (quite sure this is OK for the forcing signal with the extra buffers). For the main reference I would consider something like 50-100 ohms in series with some 10-100 nF as a little support, but without negative effect on the stability.

My plan was to get the 10V OP stable and then remove the 3u3 and the 220pF from the circuit and test. Then perhaps add 100 Ohms and 1nF at the ADC end.  I've not got far down that path 

[MiDi]

Divider of Out-10k-NFB-10k-Gnd gives gain of 2, Out-10k-NFB-25k-Gnd gives gain of 1.4.
The more gain, the more phase margin the op has.
The more capacitance at the output, the more phase margin the op has.
If I got you right, this is the behaviour shown.

[rigrunner]

Divider of Out-10k-NFB-10k-Gnd gives gain of 2, Out-10k-NFB-25k-Gnd gives gain of 1.4.
The more gain, the more phase margin the op has.
The more capacitance at the output, the more phase margin the op has.
If I got you right, this is the behaviour shown.

Yes, 2x and not unity. My error 

I have progress, of sorts.

Take the OP177, S102 and 10nF off the main board and place them on a separate PCB and the oscillation completely vanishes.
Could the PCB layout itself cause the oscillation?

Here are the spikes at the ADC input of 10VREF into the MAX312 switch. All capacitance on the output removed and also no 220pF across the OP inputs.

[Kleinstein]

The OP177 is not really fast and usually not prone o oscillation even with a really poor layout / breadboard.
A weakness of essentially all slow OPs is the PSRR for the negative side. So negative side decoupling is often more important than positive side.

It is rather difficult to get a layout so poor that it oscillates with such a slow OP. It can happen with some hidden capacitive load ( > 1 nF)  and maybe extra gain from following stages. So if the OP27 based buffers at the output of the amplifier get instable an oscillate, this may effect the OP177. Similar there could be oscillation already with the reference circuit.

The 10 K (1 mA) load from the inverting part is usually more like a good thing for the first stage.


The spikes without any capacitance  are quite large. It is not such a surprise as the OP177 is rather slow (and thus high closed loop output impedance) and the max312 switches have quite some charge injection (~ 50 pC at +-10 V). To at least limit the hight of the spike one could have a capacitor with a resistor in series. The peak would be smaller, though longer.  In theory one could have the 2 unused switches of the max313 to switch opposite polarity to compensate some of the charge pulse and also the average current with a resistor (some 100 K) to ground.
Besides the charge injection there is also the capacitance at resistors.

[rigrunner]

The OP177 is not really fast and usually not prone o oscillation even with a really poor layout / breadboard.
A weakness of essentially all slow OPs is the PSRR for the negative side. So negative side decoupling is often more important than positive side.

It is rather difficult to get a layout so poor that it oscillates with such a slow OP. It can happen with some hidden capacitive load ( > 1 nF)  and maybe extra gain from following stages. So if the OP27 based buffers at the output of the amplifier get instable an oscillate, this may effect the OP177. Similar there could be oscillation already with the reference circuit.

The 10 K (1 mA) load from the inverting part is usually more like a good thing for the first stage.

The reference is stable and quiet. The 10VREFBUF and both of the negative OPs showed only a very small amount of the oscillation they were seeing from the 10V input.

Edit: The charge injection comment has me wondering if it is worth changing the max312 to something else? A different quad switch or individual FETs?

The main PCB layout is attached, along with the daughter board that removes the oscillation.
(The PCB is nasty with flux. I know, I know, but I was only cleaning the DIP area between IC swaps.)

Would the PSRR of the negative rail be mitigated somewhat by having a single supply 0-15V for the OP instead of the +/-15V dual?

The spikes without any capacitance  are quite large. It is not such a surprise as the OP177 is rather slow (and thus high closed loop output impedance) and the max312 switches have quite some charge injection (~ 50 pC at +-10 V). To at least limit the hight of the spike one could have a capacitor with a resistor in series. The peak would be smaller, though longer.  In theory one could have the 2 unused switches of the max313 to switch opposite polarity to compensate some of the charge pulse and also the average current with a resistor (some 100 K) to ground.
Besides the charge injection there is also the capacitance at resistors.

Those spikes were visible in the DMM measurements, it made them extremely jumpy. Placing a 100 Ohm in series with the 10V ref and either a 1nF or a 10nF film after the new resistor to REFGND reduces the spikes and returns the DMM readings to normal.

Edit: Your charge injection comment has me wondering if changing the max 312 to another part, or individual FETs would be beneficial?

[Kleinstein]

Lower resistance switches have more charge injection. In this respect the max312 is not that bad - this is just the level of charge injection one has to live with, for R_on in the 10 Ohms range. I know no more suitable replacement.  Using idividual fets like in the Solartron or the new KS 3446x is quite some effort and it is not sure they are actually better. The supply to the max312 /313 needs good decoupling. Using a second part of switches for an invertes signal could be worth it. It would compensate much of the spikes and the overall reference current would be independent from the modulation, with always  one resistor active. Using a 0 and 15 V supply could help a little, like good decoupling. The difference to a more normal +-15 V supply would not be very large, unless the supply has a low of crap signal. It still help reducing the heat.

[rigrunner]

The supply to the max312 /313 needs good decoupling. Using a second part of switches for an invertes signal could be worth it. It would compensate much of the spikes and the overall reference current would be independent from the modulation, with always  one resistor active. Using a 0 and 15 V supply could help a little, like good decoupling.

I am adding decoupling to the two max ICs.

In the attached circuit part I have connected the unused part of the max313 to switch the opposite reference polarity to that being used by the integrator to ref ground via another 100K resistor. Is this what you had in mind by switching an inverted signal?

The difference to a more normal +-15 V supply would not be very large, unless the supply has a low of crap signal. It still help reducing the heat.

The -15V rail is noisy, but not too bad. Heat might be a thing to worry about if the reference and buffers are moved to the ADC board.

[Kleinstein]

The inverted switching looks like I suggested. The capacitors in parallel to the 100 ohms resistors likely don't help.

If heat is a problem and with a new PCB, one could replace the OP177 with a lower power (and lower noise) OPA207, OPA202 or ADA4077. These are also a little faster and may thus settle faster. For the inverter part an AZ OP like LTC2057 / OPA189 could be worth considering.

The reference buffers for the forcing signal would also use lower power chips than the OP27. Here DC precision is less critical.

The old PCB show a series resistor to the LTZ1000 ref. This is good and could be used for some low pass fitlering (have a capacitor of a few µC to ground). The 200 Hz range noise from the reference would add to the ADC noise (not much compared to this ADC, but still avoidable).

[rigrunner]

The inverted switching looks like I suggested. The capacitors in parallel to the 100 ohms resistors likely don't help.

Capacitors removed.

Attached is the comparator section of the ADC as it stands with IC1 changed, the slope amplifier in place, added decoupling and the multiple options for the front end resistors.

Anything broken or need changing?

If heat is a problem and with a new PCB, one could replace the OP177 with a lower power (and lower noise) OPA207, OPA202 or ADA4077. These are also a little faster and may thus settle faster. For the inverter part an AZ OP like LTC2057 / OPA189 could be worth considering.

The reference buffers for the forcing signal would also use lower power chips than the OP27. Here DC precision is less critical.

The case of the 8081 gets toasty, some 13C above ambient most of the time. The mains transformers run very warm and are the main cause of the case temperature. I'm not too concerned about physical IC temperatures but localised heating of the ADC PCB.

The old PCB show a series resistor to the LTZ1000 ref. This is good and could be used for some low pass fitlering (have a capacitor of a few µC to ground). The 200 Hz range noise from the reference would add to the ADC noise (not much compared to this ADC, but still avoidable).

I'll add pads for low pass here if/when I move the reference parts to the ADC board.

[Kleinstein]

Most of the circuit looks sensible.  The +-2.5 V supply should have more 200 Ohms - the TL431 would not be happy with so much current. One could consider to use additional resisistrs for the choice of input voltage (5 V or 15 V) instead of the suggested solder bridges.

The comparator switch level, especially for the upper LM311 may want an adjustment. So not the 100 K to pin3, but pin 3 to ground. Because of the gain in front the levels may be better a bit more separated. So maybe something like 1 K or 2.2 K and 100 K for the dividers. One would not need the same separation, as in the original, as much of the separation was likely just there to make sure the offsets of the LM311 do not cause trouble. It still helps if the integrator has reasonable settled in the time in between. Still the linear range of the slope amplifier is limtied.

Saving on the power makes sense if easy, like using lower power, more modern OPs (e.g. an OPA209 instead of the OP27).

[rigrunner]

Most of the circuit looks sensible.  The +-2.5 V supply should have more 200 Ohms - the TL431 would not be happy with so much current. One could consider to use additional resisistrs for the choice of input voltage (5 V or 15 V) instead of the suggested solder bridges.

The datasheet suggests operating range between 1 - 100mA.  I thought the 200 Ohms was a reasonable starting point.
I'll increase the 200 Ohm to 510 Ohm.  5mA @ 5V and 25mA @ 15V. If I chose to stick with the 15V supply I can change the 510 out for 2k4.

The comparator switch level, especially for the upper LM311 may want an adjustment. So not the 100 K to pin3, but pin 3 to ground. Because of the gain in front the levels may be better a bit more separated. So maybe something like 1 K or 2.2 K and 100 K for the dividers. One would not need the same separation, as in the original, as much of the separation was likely just there to make sure the offsets of the LM311 do not cause trouble. It still helps if the integrator has reasonable settled in the time in between. Still the linear range of the slope amplifier is limtied.

I've added a resistor to create a new divider for IC3 pin 3. I've used the isolated GND that IC4 uses for its divider.

Two questions came to mind when tweaking this part.

1) Do both IC3 and IC4 dividers require sub 15ppm TCR resistors to keep them reasonably stable?
2) Would a trimmer potentiometer be of any use for these dividers to allow adjustment?

Saving on the power makes sense if easy, like using lower power, more modern OPs (e.g. an OPA209 instead of the OP27).

Done. OPA209 are slightly lower cost that OP27 too