While waiting for the new pcbs i thought about the mentioned paper
https://www.wellesu.com/10.1142/s021947750700388x and tried to see whether it could potentially provide an interesting path.
However, some questions came up reading it:
Taking the square root of the used Power spectral density gives the usual Noise Spectral density, right? V²/Hz -> nV/sqrt(Hz)
They only mention/calculate the white noise contribution of the used voltage reference, current setting resistor and the dynamic diode resistances.
Yet their calculations seem to correspond to their measured curves in Figure 7, while they are working clearly inside the 1/f noise region. Cant make sense of that.
How did they arrive at the mentioned 8 x 10^-17 V²/Hz spec for the used AD586?
Attached is a general first idea how it could be implemented.
ADR1399 7.05V *2 gain stage provides the necessary >10V reference voltage.
The transistor stage Q1/Q4 provides the current to the diodes, without loading the OPA189.
The original SSM2220 are obsolete, but THAT320 arrays or similar should also be suitable.
Then again i just opted to go for 12x ZTX951 transistors (lowest noise according to AoE3, about 1€/piece) attached to a temp controlled aluminium core pcb, which would sit inside the already temp controlled chamber mentioned a few posts earlier.
The 12x diode connected transistors provide the wanted 10Vout by adjusting the flowing current through them, the heater stage keeps the 10V stable by minimizing the diode TC.
The paper only mentioned the equivalent diode resistance and doesnt go into depth about 1/f noise contribution of diode connected transistors, so i just thought its best to use low noise (low rbb) transistors for this job.