An experimental PWM circuit with 74HCU04

[arvee]

This is my first post on this forum.
Here is another PWM circuit.

The switching is done by the 74HCU04 hex unbuffered inverter.
The PMOS and NMOS transistors of this inverter have low on-resistance (25 ohms).
Logic inverters are normaly optimized for speed.
The good news is that here the on-resistance of the transistors is well matched.
With six parallel inverters the measured resistances are: PMOS 4.07 ohm, NMOS 3.79 ohm.
The difference in only 0.28 ohm.

The reference voltage is made with an LM399, the nominal voltage is 7 volt, and 1 ppm is 7 uV.

The low-pass filter has resistor 50k ohm and capacitor 1 uF.
The error is parabolic and the maximum INL is 0.28 ohm / 50k ohm / 4 = 1.4 ppm.

The Arduino clock frequency is 16 MHz.
The PWM frequency is 300 Hz (divide by 53333).
The length of the sigma-delta modulation is 300.
With an integration time of the DMM of one second the resolution is 24 bit.

Everything is as simple as possible. There is no output buffer or extra filtering.
The load of 10M ohm decreases the output voltage but has little effect on the linearity.
The first-order filter has limited attenuation at 300 Hz, but the normal mode rejection of the meter of 60 dB helps.
With an integration time of 1 or 2 seconds there is sigma-delta ripple is averaged out.

The output voltage is measured with an HP34401A.

[DeltaSigmaD]

Thanks for showing the circuit. Certain improvements are possible with minor modifications.

-  The PWM frequency of 300Hz is very low, so that very long time for averaging is required. With a 16MHz uC, a PWM frequency above 200kHz is possible, including DS update with this rate. A PWM frequency >20 kHz should be no problem with suitable software.

-  A lowpass of order >=3 and a buffer amplifier are necessary to use the circuit as controllable reference e.g. for calibration. 

-  The reference buffer must have very good dynamic characteristics for high DAC linearity. Your buffer amplifier circuit shows deviations of 1.9 mVpp with a 1mA load step and an output impedance of 1 Ohm. With a small modification (please see below), the deviation can be reduced to <0.3 mVpp, and the output impedance is <0.17 Ohm always, a further improvement is easy.

[arvee]

I forgot to mention that the SN74HCU04 is from Texas instruments. Mine has date code October 2019.

The measured results are not so bad. The plots are a full sweep from 0 to approximately 7 volt.

Parabolic error is 2.02 ppm. It should have been 1.4 pmm, but there is a wire with resistance  0.1 ohm between buffer and inverter.

The error from duty cycle error is 0.7 pmm. That is 2.3 ns of the period of 3300 us. This error is visible at the beginning and end of the sweep.

After the numeric correction it becomes boring with mostly the noise of the meter.
 

[Andreas]

-  The PWM frequency of 300Hz is very low, so that very long time for averaging is required. With a 16MHz uC, a PWM frequency above 200kHz is possible, including DS update with this rate. A PWM frequency >20 kHz should be no problem with suitable software.

My experiences are different: the higher the switching frequency the more bad are the temperature dependant  and unsymmetrically rise and fall times.
300 Hz is a optimized frequency which will be filtered out together with mains frequency suppression (above 1 NPLC 50 or 60 Hz).

Parabolic error is 2.02 ppm. It should have been 1.4 pmm, but there is a wire with resistance  0.1 ohm between buffer and inverter.

That is really a good result.
with a single analog switch (74HCT4053) I had around 0.5-0.6 mV / 5V so around 100-120 ppm parabolic error.
But you know that the 7V is at the maximum rating for the poor HCU04?

with best regards

Andreas

[arvee]

The decoupling capacitor of the inverter is 10 µF. It has 1 ohm in series because that is the ESR of the tantalum capacitor.

The buffer sees current pulses from the switching of the output inverter.
The charge of one pulse can be estimated from the "power dissipation capacitance" CPD = 10 pF.
Or you can measure the average current with 10kHz switching frequency.

There are six inverters. The charge of one transition is Q = CPD*VDD = 10pF*7V*6/2 = 210 pC.
For example a pulse with height 21 mA and width 10 ns.

Over the 1 ohm ESR resistor of the decoupling capacitor this makes a voltage pulse of 21 mV, with area 210 pVs.
The clock frequency is 16 MHz and the minimum width is 62.5 ns, and with 7 volt the area is 437.5 nVs.
The effect of current spikes is very small and it is not needed to remove them with a faster buffer.

There is a low pass filter in the feedback to be sure that voltage spike reduce at the input of the bipolar differential pair.

The buffer can be made with op amps. The amplifier which drives the output must be fast with 10 MHz unity-gain bandwidth. I think the circuit can still be improved, but this is what I have.

The maximum rating of 7 volt should not be a big issue. Perhaps there is long time degradation. The alternative is to use a 5V voltage reference.

[RoGeorge]

Nice results!   

If 300Hz is not enough, then using PDM (Pulse Density Modulation) might worth considering.

A software PDM is very easy to implement, can be easily extended to more than 16 bits, and the pulses are narrower than those coming from a PWM, so the analog filter might give better results for PDM than for PWM.

I did a small demo once, the PDM itself needs only 5 lines:
https://hackaday.io/project/6356-delta-sigma-versus-pwm
https://github.com/RoGeorge/Delta-Sigma_versus_PWM

[MegaVolt]

A software PDM is very easy to implement, can be easily extended to more than 16 bits, and the pulses are narrower than those coming from a PWM, so the analog filter might give better results for PDM than for PWM.

It looks like DDS.