I was under the wrong impression that the D1281 is no chopper design, but uses the 2N4117 as slow autozero-switches (as in 100NPLC -> 2s measurement of input, 2s measuring offset).
Cant find the Clock-L frequency in the manual, maybe i should run an OCR-tool across the pdf to make it searchable...meh.
Attached a D1281 simulation, which doesnt yet work.
Youre right, the high bridge-resistance completely completely destroys the low-current-noise-approach with its thermal-noise of 128nVrms -> ~850nVpp for a bridge consisting of 4x 100k-resistors alone.
So either a slow-chopped low noise JFET-OP like OPA140 + an additional gain OP or a discrete JFET-frontend like D1281...which looks nice since its already designed and working.
Dont know if id need the bootstrap-supply though for increased CMRR in this situation?
During playing with my K155 i found that it doesnt have 0.1-10Hz-spec, but instead a specced rise-time of 5s at the 1µV-range which roughly explains the measured noise of ~900nVpp (measured with 34465A at K155 analog output over half an hour) measured at an 900kR-resistor.
Is an amplifier-concept which uses a slow automatic offset compensation possible, which would short the input every 10s and then after measuring offset it would be automatically compensated?
Edit: Attached working simulation of a chopper taken from
http://www.janascard.cz/PDF/Design%20of%20ultra%20low%20noise%20amplifiers.pdf page 8. Need to attach D1281_simulation...
Edit2: Attached non working simulation chopper taken from
https://www.eevblog.com/forum/metrology/low-frequency-noise-of-zero-drift-amplifiers/?action=dlattach;attach=663045