What is the purpose of such op-amp connection?

[labmaxtver]

Hello everybody.
In attachment there is a diagram of ADC, used in laboratory scales. 1978, but pretty good.
ADC is 18+ bit, delta-sigma. D9 with 0.15u capacitor, 16.4 and 7.4k resistors work as an integrator. For some purposes it's output was connected to common-base transistor circuit with a current source as a load. Why?
First I thought it was done to stabilize operation point of the op-amp (thermal drift reduction). But then I calculated - 5uV/^oC (max.) for LF355 makes ADC error only 0.15 LSB per ^oC - 7 times less then required by specs.
My second idea was about linearity. Maybe engineers decided to shut down upper part of op-amp's output, when all it's used transistors work in linear mode. This IC is exellent for 1978: JFET input, max 5uV/^oC, 2V/us, 2,5MHz, and 10⁵ gain. Gain... Maybe, a good idea is to specify not only open-loop voltage gain, but also offset voltage VS load current?
OK. If load is set at point, when op-ap becomes "high-end", and the bias voltage is proportional to the load current, I expect fixed bias step when reference source connected/disconnected. The input voltage does not affect this bias. ADC equation shows, that it would be linear only when resistors of Vx and Vref were equal. But they not.
Of cause, if bias dependencies on output current are different for positive and negative load, the ADC equation is more complicated and nonlinear.
But again... Scales got linearity adjustment circuit, which affects all system - from weighting plate to display.

I can't understand why D9 was placed in such circuit. Why 0.15u capacitor was simply not connected to it's pin 6? What is the reason?

(eight resistors with switches are used for brutal calibration)

[Kleinstein]

The transistor and current source together work like a rather fast amplifier.  The overall circuit is similar to the integrator used in many modern multi-slope ADCs, like in the Keithley 2000 or HP34401.
The transistor and current source part replaces U1B in the attached schematics of the 2 amplifier integrator.

The idea behind the 2 OP-amp integrator is to have the amplifier A to correct the input voltage closer to zero. With just a single OP-amp the input votlage would still have some residual input voltage of  input current divided by (2 Pi*GBW*capacitance ). This gives rise to a small nonlinear error.  U1A deternines the accuracy, while U1B mainly has to be fast.

The intergrator circuit looks very much like the one used in the Prema DMMs.

[labmaxtver]

Thank you!
In other words - simple integrator can't accurately reproduce rising and falling lines of triangle because of limited bandwidth, so it has some additional impedance Z=1/(2Pi*f_BGW*C) at a point of OP-amp input? I understood you correctly?
In this case, for my circuit (with simple integrator), equation will be:
                             U_xR_ref(1-Z/R_x)
Duty Cycle = ---------------------------------- , where Z, R_x, R_ref, U_ref are constants, dependence of Duty Cycle from Ux is nonlinear, OK
                      U_ref(R_x-Z(1+R_x/R_ref))+ZU_x
In my case, Rx and Rref are different and Ux is connected constantly.
But the circuit (attachment) of Prema multimeter (with the same integrator circuit) works another way. Here there is only one resistor and input connects with Ux and Uref in turn.
I think, this is a simple double-integrating ADC, with fixed period of charge (Tx), and measured discharge period (Ty) proportional to Ux (algorithm of measuring duty cycle in this case will be absolutely nonlinear).
t_xI_x=T_yI_y, T_y=T_x(I_x/I_y)
Currents will be: I_x=U_x/(R+Z), I_y=U_ref/(R+Z)
The denominators are the same and cancel, so equation for Prema ADC:
T_y=T_xU_x/U_ref, linear, does not depend on GBW.
I now don't speak about extra high section frequency (or low RC) of differentiator. In two-OPs integrator circuit, amplifier's inverse inputs connected directly for DC.
That's why, maybe Prema ADC uses this circuit for some other purposes?

[Kleinstein]

The picture with the extra impedance at the integrator input is also my understanding. Ideally this is not a problem if the resistance for the integrator input is constant (e.g. matched resistors for pos. and neg. reference). However no matching is perfect and the effective GBW of the integrator OP does change with load current. The cases of positive and negative load current to an OP-amp see different output stages and thus potentially slightly different GBW. The cross over region add extra complications.

Especially in the old circuits there is another reason: precision OP-amps (e.g. OP07, OPA177, AD707, ICL7650)  were traditionally slow and the 2nd amplifier speeds up the settling at the integrator input. The 2nd amplifier can be fast, but no need for precision. The integrator input still sees a voltage peak after the reference is switched, but these voltage peaks happen under fixed conditions with the same references active. So as long as the modulation frequency is constant, this would only be a fixed offset and indirectly maybe a slight change in the gain.
The HP34401 uses the OP27 as a fast precision amplifier, but this comes with quite some current noise - still OK for the 34401 as there are other noise sources that are even worse (though not much).

The prema circuit has a fixed input resistance to the integrator and would ideally not be effected by the extra impedance (as long as this is constant). AFAIR they add the reference voltage with a switched capacitor to the input voltage.  So it is not either input or reference voltage (like in a dual slope ADC), but always the input and plus or minus the reference from a flying capacitor.  This also helps with a stable gain as the same resistor is used. The more classical multislope ADC with separate resistors gets an extra resisstor ratio entering the ADC gain. The downside is the extra effort and possible errors (e.g. from charge injection at the switches) from adding the reference voltage to the input voltage.

I don't see a 2nd integrator in the prema circuit - the 10 nF capacitor towards the base is mainly to avoid low frequency current from the base to effect the integrator. The relevant frequencies there are like the ADCs response and thus mainly the very low frequency part (e.g. < 30 Hz). A 2nd integrator would be more between the 1st integrator and the comparartor. AFAIK the 2nd integrator would be less critical and no special needs there. My guess is they use the extra transistor to speed up the integator and still get away with the rather slow OP07.
There is one point in the 2 OP-amp circuit, not given by the transotor circuit: the 1 st amplifier that is relevant for the precision still sees the variable load current (though a rather constant ouput voltage and one sign current). In the 2 OP-amp circuit the 1st amplifier sees very little load, which helps with supply decoupling.

[labmaxtver]

GBW of the integrator OP does change with load current. The cases of positive and negative load current to an OP-amp see different output stages and thus potentially slightly different GBW. The cross over region add extra complications.

At this side we came to a consensus. To prevent current of another polarity  and cross-region is a good decision.

The integrator input still sees a voltage peak after the reference is switched, but these voltage peaks happen under fixed conditions with the same references active. So as long as the modulation frequency is constant, this would only be a fixed offset and indirectly maybe a slight change in the gain.

Yes, I think 10n capacitor was used to reduce peak. Really, before OP-amp reacted, output impedance of this circuit is very high, much more than input resistors. But than it begins work in common-emitter mode.
My circuit modulated at 256 Hz and measuring cycle 128 periods (0.5s). That's right, but I think peaks make some noise.

My guess is they use the extra transistor to speed up the integrator and still get away with the rather slow OP07.

You mean to speed up setting at the integrator input after reference switching? In other case (for example my circuit) RC of 10n with 10 and 18k parallel (I do not look at transistor base impedance in common-emitter mode - it will be much lower) is 64us, when average length of reference pulse is 600us, max. 1200. I don't think it's enough to make something with GBW-related bias.

[Kleinstein]

For the circuit it would make sense to run a Spice simulation. Most of the parts should simulation OK, maybe except some details of the charge injecition at the JFETs.

The voltage peaks at the integrator input alone don't cause much noise. The trouble there is more with phases that are rather short and the reference already switching before the integrator input is fully settled.
I don't like the reference swiching part very much: when off the switch node is only coupled via the resistor to the integrator. This gives quite some change in resitance for the integrator input and thus the need for the 2 amplifiers.
The modulation frequency is also quite low and thus not too many switching events to cause noise and a reasonable time for settling. There are several parts that don't look really low noise and high linearity. The LF355 is a rather fast amplifier, but not known for precision or low noise.  Another somewhat nasty part is the delay caused the BJTs to switch the JFETs. The variable load to the reference vottage can also be a problem. That reference part looks somewhat odd. 

[labmaxtver]

For the circuit it would make sense to run a Spice simulation.

I don't have LTspice, but made a simulation some time ago. It works in browser. Problem that OP-amp there is ideal, with only gain adjustable. There is 741 with rising time adjustment, but to simulate LF355 I need to put JFETs before it's inputs - this is to much and he gives error message. Simulation with simplified digital part and reference (as a switch used ideal CMOS output with 7V suply of IC):
https://tinyurl.com/2nj8vng6

The trouble there is more with phases that are rather short and the reference already switching before the integrator input is fully settled.

You mean if Ux is low and reference pulse is short - time is not enough? I agree. It will cause nonlinearity, but I hope - stable nonlinearity, which can be corrected by compensator.

Regardless, scales work fine. The ADC range is 30g (if more they automatically use weights with 20g step, 170g total capacity), scales show 0.0001g and it "costs" exactly 1 pulse per 0.5s cycle. No extra bits, and the last symbol is pretty stable! Of cause, controller calculates average of last 2, 4 or 8 cycles - what you need - stability or speed.
There are some other problems.

[labmaxtver]

As far as I understand, slew rate primarily decreases with:
- increasing of common-emitter stages number;
- increasing of amplitude on collectors of such stages.
I made a picture of LF355 internal structure (attachment 1) with external transistor and current source (blue). Output protection and null adj. circuits are erased. Red transistor is closed, works only on setting time.
At the bottom we see something like Sziklai pair, with p-JFET as p-n-p transistor in classic Sziklai pair. It follows voltage on output of differential stage. Because of very low amplitude on exit, provided by common-base external circuit, amplitude on differential stage exit is also low. In such small signal regime the role of internal compensation (especially C2) also declines.
It would be better to use upper part, because no common emitter there. But if we look at OP07 structure (attachment 2) - bottom part is p-n-p and common collector. OP07 about 10 times slower, than LF355, so I think Prema circuit was designed to increase it's slew rate.
Sartorius produces scales, not voltmeters. Probably they bought this circuit from some patent. Or maybe circuit first was designed to use OP07, but then it was just replaced with LF (same case and pinout)  for some reasons.
I remember audio circuit of Deutsch (DDR) ham, who used very similar idea to make slow A109 OP-amp faster (attachment 3).

[David Hess]

I thought of a reason they did that.  I have seen the same thing in a Solartron design and now it makes sense.

Because of the current source and transistor, the LF335 output is held at a constant voltage and constant current, so its power dissipation is constant.  If the output current or voltage was allowed to change, then changes in heating of the die would cause offset voltage changes and lower open loop gain, limiting precision.  Open loop gain in an operational amplifier is primarily limited by thermal feedback from the output transistors to the input transistors.

Circuits using precision operational amplifiers often take steps to minimize the output load to retain precision, or go to the same extreme shown here.

[Kleinstein]

The current seen by the OP-amp is not constant, but only constant on average, which is enough not to effect the temperature too much.
The LF355 is not a high precision OP - so the self heating is more like a smaller problem and the OP07 could well be the better choice, though slower. It may be a cost factor / BOM simplification.

The slew rate is not so much the relevant limit. It is more the GBW that is relevent for the integrator, though one needs to stay away from the slow rate limit. The slew rate is usually limited by the current the input stage can deliver and the capacitor used for compensation. The number of transistors in emitter circuit is not relevant - it is more the slowest part beside the stage used for the compensation that limits the maximum useful bandwidth of the amplifier circuit.

The JFET based amplifiers often have a relatively high slew rate relative to there BW as the input stage needs a higher voltage at the input to get the full output current. With no base current to cause bias current,  the input stage can run with a relatively high current with not much negative effect. BJT based differential stages usually saturate at some 50 mV differential and it takes additional emitter degeneration to raise that limit.