Electronics > Metrology
What is the purpose of such op-amp connection?
labmaxtver:
Hello everybody.
In attachment there is a diagram of ADC, used in laboratory scales. 1978, but pretty good.
ADC is 18+ bit, delta-sigma. D9 with 0.15u capacitor, 16.4 and 7.4k resistors work as an integrator. For some purposes it's output was connected to common-base transistor circuit with a current source as a load. Why?
First I thought it was done to stabilize operation point of the op-amp (thermal drift reduction). But then I calculated - 5uV/oC (max.) for LF355 makes ADC error only 0.15 LSB per oC - 7 times less then required by specs.
My second idea was about linearity. Maybe engineers decided to shut down upper part of op-amp's output, when all it's used transistors work in linear mode. This IC is exellent for 1978: JFET input, max 5uV/oC, 2V/us, 2,5MHz, and 105 gain. Gain... Maybe, a good idea is to specify not only open-loop voltage gain, but also offset voltage VS load current?
OK. If load is set at point, when op-ap becomes "high-end", and the bias voltage is proportional to the load current, I expect fixed bias step when reference source connected/disconnected. The input voltage does not affect this bias. ADC equation shows, that it would be linear only when resistors of Vx and Vref were equal. But they not.
Of cause, if bias dependencies on output current are different for positive and negative load, the ADC equation is more complicated and nonlinear.
But again... Scales got linearity adjustment circuit, which affects all system - from weighting plate to display.
I can't understand why D9 was placed in such circuit. Why 0.15u capacitor was simply not connected to it's pin 6? What is the reason?
(eight resistors with switches are used for brutal calibration)
Kleinstein:
The transistor and current source together work like a rather fast amplifier. The overall circuit is similar to the integrator used in many modern multi-slope ADCs, like in the Keithley 2000 or HP34401.
The transistor and current source part replaces U1B in the attached schematics of the 2 amplifier integrator.
The idea behind the 2 OP-amp integrator is to have the amplifier A to correct the input voltage closer to zero. With just a single OP-amp the input votlage would still have some residual input voltage of input current divided by (2 Pi*GBW*capacitance ). This gives rise to a small nonlinear error. U1A deternines the accuracy, while U1B mainly has to be fast.
The intergrator circuit looks very much like the one used in the Prema DMMs.
labmaxtver:
Thank you!
In other words - simple integrator can't accurately reproduce rising and falling lines of triangle because of limited bandwidth, so it has some additional impedance Z=1/(2Pi*fBGW*C) at a point of OP-amp input? I understood you correctly?
In this case, for my circuit (with simple integrator), equation will be:
UxRref(1-Z/Rx)
Duty Cycle = ---------------------------------- , where Z, Rx, Rref, Uref are constants, dependence of Duty Cycle from Ux is nonlinear, OK
Uref(Rx-Z(1+Rx/Rref))+ZUx
In my case, Rx and Rref are different and Ux is connected constantly.
But the circuit (attachment) of Prema multimeter (with the same integrator circuit) works another way. Here there is only one resistor and input connects with Ux and Uref in turn.
I think, this is a simple double-integrating ADC, with fixed period of charge (Tx), and measured discharge period (Ty) proportional to Ux (algorithm of measuring duty cycle in this case will be absolutely nonlinear).
txIx=TyIy, Ty=Tx(Ix/Iy)
Currents will be: Ix=Ux/(R+Z), Iy=Uref/(R+Z)
The denominators are the same and cancel, so equation for Prema ADC:
Ty=TxUx/Uref, linear, does not depend on GBW.
I now don't speak about extra high section frequency (or low RC) of differentiator. In two-OPs integrator circuit, amplifier's inverse inputs connected directly for DC.
That's why, maybe Prema ADC uses this circuit for some other purposes?
Kleinstein:
The picture with the extra impedance at the integrator input is also my understanding. Ideally this is not a problem if the resistance for the integrator input is constant (e.g. matched resistors for pos. and neg. reference). However no matching is perfect and the effective GBW of the integrator OP does change with load current. The cases of positive and negative load current to an OP-amp see different output stages and thus potentially slightly different GBW. The cross over region add extra complications.
Especially in the old circuits there is another reason: precision OP-amps (e.g. OP07, OPA177, AD707, ICL7650) were traditionally slow and the 2nd amplifier speeds up the settling at the integrator input. The 2nd amplifier can be fast, but no need for precision. The integrator input still sees a voltage peak after the reference is switched, but these voltage peaks happen under fixed conditions with the same references active. So as long as the modulation frequency is constant, this would only be a fixed offset and indirectly maybe a slight change in the gain.
The HP34401 uses the OP27 as a fast precision amplifier, but this comes with quite some current noise - still OK for the 34401 as there are other noise sources that are even worse (though not much).
The prema circuit has a fixed input resistance to the integrator and would ideally not be effected by the extra impedance (as long as this is constant). AFAIR they add the reference voltage with a switched capacitor to the input voltage. So it is not either input or reference voltage (like in a dual slope ADC), but always the input and plus or minus the reference from a flying capacitor. This also helps with a stable gain as the same resistor is used. The more classical multislope ADC with separate resistors gets an extra resisstor ratio entering the ADC gain. The downside is the extra effort and possible errors (e.g. from charge injection at the switches) from adding the reference voltage to the input voltage.
I don't see a 2nd integrator in the prema circuit - the 10 nF capacitor towards the base is mainly to avoid low frequency current from the base to effect the integrator. The relevant frequencies there are like the ADCs response and thus mainly the very low frequency part (e.g. < 30 Hz). A 2nd integrator would be more between the 1st integrator and the comparartor. AFAIK the 2nd integrator would be less critical and no special needs there. My guess is they use the extra transistor to speed up the integator and still get away with the rather slow OP07.
There is one point in the 2 OP-amp circuit, not given by the transotor circuit: the 1 st amplifier that is relevant for the precision still sees the variable load current (though a rather constant ouput voltage and one sign current). In the 2 OP-amp circuit the 1st amplifier sees very little load, which helps with supply decoupling.
labmaxtver:
--- Quote from: Kleinstein on June 24, 2022, 06:31:43 pm ---GBW of the integrator OP does change with load current. The cases of positive and negative load current to an OP-amp see different output stages and thus potentially slightly different GBW. The cross over region add extra complications.
--- End quote ---
At this side we came to a consensus. To prevent current of another polarity and cross-region is a good decision.
--- Quote from: Kleinstein on June 24, 2022, 06:31:43 pm ---The integrator input still sees a voltage peak after the reference is switched, but these voltage peaks happen under fixed conditions with the same references active. So as long as the modulation frequency is constant, this would only be a fixed offset and indirectly maybe a slight change in the gain.
--- End quote ---
Yes, I think 10n capacitor was used to reduce peak. Really, before OP-amp reacted, output impedance of this circuit is very high, much more than input resistors. But than it begins work in common-emitter mode.
My circuit modulated at 256 Hz and measuring cycle 128 periods (0.5s). That's right, but I think peaks make some noise.
--- Quote from: Kleinstein on June 24, 2022, 06:31:43 pm ---My guess is they use the extra transistor to speed up the integrator and still get away with the rather slow OP07.
--- End quote ---
You mean to speed up setting at the integrator input after reference switching? In other case (for example my circuit) RC of 10n with 10 and 18k parallel (I do not look at transistor base impedance in common-emitter mode - it will be much lower) is 64us, when average length of reference pulse is 600us, max. 1200. I don't think it's enough to make something with GBW-related bias.
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