I got something kludged together to generate ~9KHz pulses on PA1
Used your CCP as base
/*--------------------------------------------------*/
void system_init(void)
{
LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz);
while (LL_RCC_HSI_IsReady() != 1);
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA | LL_IOP_GRP1_PERIPH_GPIOB | LL_IOP_GRP1_PERIPH_GPIOF);
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1);
// LL_GPIO_Init(SWC_Port, &(LL_GPIO_InitTypeDef){ SWC_Pin, LL_GPIO_MODE_ANALOG }); // Disable SWD interface access
// LL_GPIO_Init( SWD_Port, &(LL_GPIO_InitTypeDef){ SWD_Pin, LL_GPIO_MODE_ANALOG });
LL_GPIO_Init(CCP_Port, &(LL_GPIO_InitTypeDef){ CCP_Pin, LL_GPIO_MODE_ALTERNATE, LL_GPIO_SPEED_FREQ_VERY_HIGH, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PULL_NO, CCP_AF });
LL_GPIO_Init(RED_Port, &(LL_GPIO_InitTypeDef){ RED_Pin, LL_GPIO_MODE_OUTPUT, LL_GPIO_SPEED_FREQ_VERY_HIGH, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PULL_NO });
LL_GPIO_Init(GREEN_Port, &(LL_GPIO_InitTypeDef){ GREEN_Pin, LL_GPIO_MODE_OUTPUT, LL_GPIO_SPEED_FREQ_VERY_HIGH, LL_GPIO_OUTPUT_PUSHPULL, LL_GPIO_PULL_NO });
LL_GPIO_Init(BTN_Port, &(LL_GPIO_InitTypeDef){ BTN_Pin, LL_GPIO_MODE_INPUT, 0, 0, LL_GPIO_PULL_UP });
//https://community.st.com/t5/stm32-mcu-products/setting-the-timer-tim1-in-stm32f407/td-p/395256
//LL_TIM_Init(CCP_TIM, &(LL_TIM_InitTypeDef){ 23, LL_TIM_COUNTERDIRECTION_UP, 65535, LL_TIM_CLOCKDIVISION_DIV1, 0}); // 1MHz clock, 65ms overflow
LL_TIM_Init(CCP_TIM, &(LL_TIM_InitTypeDef){ 11, LL_TIM_COUNTERDIRECTION_UP, 111, LL_TIM_CLOCKDIVISION_DIV1, 0}); // 1MHz clock, 65ms overflow
//LL_TIM_IC_Init(CCP_TIM, CCP_CH, &(LL_TIM_IC_InitTypeDef){ LL_TIM_IC_POLARITY_FALLING, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ICPSC_DIV1, 4 }); // Falling edge
LL_TIM_OC_Init(CCP_TIM, CCP_CH, &(LL_TIM_OC_InitTypeDef){ LL_TIM_OCMODE_TOGGLE, LL_TIM_OCSTATE_ENABLE, LL_TIM_OCSTATE_ENABLE, 111,
LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCIDLESTATE_LOW }); // Falling edge
// Generates 8.97 KHz pulses
LL_TIM_EnableCounter(CCP_TIM);
LL_TIM_CC_EnableChannel(CCP_TIM, CCP_CH);
LL_TIM_EnableAllOutputs(CCP_TIM);
NVIC_SetPriority(TIM1_CC_IRQn, 1);
//NVIC_EnableIRQ(TIM1_CC_IRQn);
SysTick_Config(24000); // 24MHz cpu clock, 1ms period.
}
But it seems like it's the below LL_TIM_Init that controls the Pulse duration
24M/12/111 ~18KHz ==> 9KHz Toggled
LL_TIM_Init(CCP_TIM, &(LL_TIM_InitTypeDef){ 11, LL_TIM_COUNTERDIRECTION_UP, 111, LL_TIM_CLOCKDIVISION_DIV1, 0}); // 1MHz clock, 65ms overflow
Whar does the 111 in this one (LL_TIM_OC_Init) do then ?
LL_TIM_OC_Init(CCP_TIM, CCP_CH, &(LL_TIM_OC_InitTypeDef){ LL_TIM_OCMODE_TOGGLE, LL_TIM_OCSTATE_ENABLE, LL_TIM_OCSTATE_ENABLE, 111,
LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCIDLESTATE_LOW }); // Falling edge
I would have expected that one :
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
To control the "compare" ...
Will try tomorrow, with the 9KHz from my F002 dev board as pulse source.
Ps:
Thank you for your examples & guidance
/Bingo
Home
Help
Search
Login
Register
