if (ADC_array_position !== ADC_array_end)
The compiler fails saying that there is nothing before "="
That’s because you’re writing C, not Verilog.
This is one of the reason why I think people who say, “If you know C, you’ll be able to pick up Verilog in no time!” Yeah, sure, despite the fact that the two languages serve different problem domains.
Here’s a fun bug that baffled me for a little bit. I was doing a project that had an 8051 talking to an FPGA. And for the micro code, I wrote something like:
if (foo /= bar) {
And wondered why it compiled, linked, but didn’t work.