Casting problem in VHDL

[ali_asadzadeh]

Hi
I'm kinda new to VHDl, I can not seems to figure out how to do this conversion, what should I do?

Code: [Select]

type myFRQ_BUF0 is array (0 to 7) of STD_LOGIC_VECTOR (47 DOWNTO 0);
signal CapVal_00,CapVal_01 : STD_LOGIC_VECTOR (47 downto 0); 
signal freerun_cnt: STD_LOGIC_VECTOR (31 downto 0); 
signal RMS_BUF0,RMS_BUF1: myRMS_BUF0;

process (clk)
begin
if rising_edge(clk) then

freerun_cnt <= freerun_cnt + '1';

if rising_edge(capture) then
CapVal_01 <= freerun_cnt;
if(CapVal_01 > CapVal_00) then
FRQ_BUF0 <= STD_LOGIC_VECTOR (unsigned(CapVal_01) - unsigned(CapVal_00));
else
FRQ_BUF0 <= STD_LOGIC_VECTOR((unsigned(CapVal_01) + X"100000000000") - unsigned(CapVal_00));
end if;
CapVal_00 <= CapVal_01;
end if;

end if;

end process;



ISE would trough this error

Near std_logic_vector ; type conversion does not match type myfrq_buf0

[ale500]

What is the FRQ_BUF0 definition ?

FRQ_BUF0 <= STD_LOGIC_VECTOR (unsigned(CapVal_01) - unsigned(CapVal_00));

[Scrts]

Your myFRQ_BUF0 is array:

Code: [Select]

type myFRQ_BUF0 is array (0 to 7) of STD_LOGIC_VECTOR (47 DOWNTO 0);


You are assigning std_logic_vector to an array. Assign it to one vector of that array then. For example to array element (0).

[ali_asadzadeh]

Thanks Scrts

[ali_asadzadeh]

I wanted to capture the duty cycle of a low speed input, it's called capture and it's about 500HZ my system clock is 50MHz, I have used chip scope to see the FRQ_BUF0(0) value, but it seems it does not capture the data correctly, I will get the FRQ_BUF0(0) some odd values like 0,2,3, 361 etc...

what's wrong with my code, I have done it in an NXP LPC timer and the code is similar to the C implementation in there.

my C code for the LPC looks like this and it works perfectly.

Code: [Select]

void TIMER2_IRQHandler(void)
{
LPC_TIMER2->IR=0XF0;//Clear all sources
CaptureValue[0][1]=LPC_TIMER2->CR0;
if(CaptureValue[0][1]>CaptureValue[0][0])
{
freq[0] = CaptureValue[0][1] - CaptureValue[0][0];
}
else
{
freq[0] = ((uint64_t)CaptureValue[0][1]+ 0x100000000) - (uint64_t)CaptureValue[0][0];
}
CaptureValue[0][0]=CaptureValue[0][1];

}


[Dago]

Are you synchronizing the input signal going to the FPGA? A 1-3 stage flip-flop chain is usually used for this.

[hamster_nz]

Code: [Select]

if rising_edge(clk) then
 
 freerun_cnt <= freerun_cnt + '1';
 
 if rising_edge(capture) then

Nested "if rising_edge(xxx)" makes no sense. It might simulate but is wrong.

 - no two signals can have a rising edge at the sametime.

- In hardware a flipflop can only be sensitive to one edge.

Also your sensitivity list is just for one signal.

[ali_asadzadeh]

Thanks I have syncronized the capture with the CLK but I still out of lock

Here is the updated code

type myFRQ_BUF0 is array (0 to 7) of STD_LOGIC_VECTOR (47 DOWNTO 0);
signal CapVal_00,CapVal_01 : STD_LOGIC_VECTOR (47 downto 0); 
signal freerun_cnt: STD_LOGIC_VECTOR (31 downto 0); 
signal RMS_BUF0,RMS_BUF1: myRMS_BUF0;
signal capture : STD_LOGIC_VECTOR(2 downto 0);

process (clk)
begin
if rising_edge(clk) then
 
 freerun_cnt <= freerun_cnt + '1';
 
 capture <= capture(2 downto 1) & capture_pin;
 if  capture(2)= '0' and capture(1) = '1' then --rising_edge capture
  CapVal_01 <= freerun_cnt;
  if(CapVal_01 > CapVal_00) then
   FRQ_BUF0(0) <= STD_LOGIC_VECTOR (unsigned(CapVal_01) - unsigned(CapVal_00));
  else
   FRQ_BUF0(0) <= STD_LOGIC_VECTOR((unsigned(CapVal_01) + X"100000000000") - unsigned(CapVal_00));
  end if;
  CapVal_00 <= CapVal_01;
 end if;
 
end if;
 
end process;

[Someone]

You cant simply rewrite sequential (C) code in VHDL syntax and have it work. Here is a really high level and shallow coverage of the basics:
http://web.mit.edu/6.111/www/f2007/handouts/L06.pdf
You need to spend some serious time learning about how a simultaneous evaluation language (non-blocking assignments in HDL) works, and why its not directly the same as sequential language. This isnt something quick and easy but many days of slow learning to completely change your point of view about what programming is.

Walk before you run.....

[Kalvin]

If your intention is to implement a shift register, the following code snippet may not do what you intend to do:

Code: [Select]

capture <= capture(2 downto 1) & capture_pin;

See here: http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html

[ali_asadzadeh]

capture <= capture(2 downto 1) & capture_pin;

It's for  synchronising the capture_pin to the FPGA clock

[hamster_nz]

capture <= capture(2 downto 1) & capture_pin;

It's for  synchronising the capture_pin to the FPGA clock

Or a little less subtly,  how does the value in capture(1) change when you keep on assigning it to itself?

Did you mean:

Code: [Select]

capture <= capture(1 downto 0) & capture_pin;