[SAMC] TC in wave generation mode

[Simon]

I'm guessing there are various events of which one could be a pin state bu there is also a default pin that avoids the event system.

[ogden]

although the CTRLA register description sounds like indeed the WO pin could also be the input capture pin:

There is no such thing as WO pin. When you look in the port multiplex table, pin (function) labels are "TCCx/WO[z]", not just "WO".

[ataradov]

It looks like they actually improved it in SAM C. SAM D series did not have it as an input. In this case it does look like it can capture from an input directly. Hallelujah.

SAM D devices could only capture the actual events from the event system. And corresponding table reflects that.

[Simon]

Am i right to assume that if i can set the pin high/low in software the pin multiplexing has not taken effect?

[ataradov]

Yes, if you still have control over the pin via OUTSET/OUTCLR, multiplexing is disabled.  When peripherals are connected they take over the corresponding control lines.

Although there are examples where you may mistake control over the pin versus control over the pull-up. For example if you enable EIC, you still have control over the pull-up/pull-down resistor if the pin is configured as an input. Externally this can be mistaken for the control over the pin.

[Simon]

Well i am trying to set the pin to work with a TC so from what you say I should not be able to toggle it. Do i need to set it as an output or does the peripheral completely take over.

[ataradov]

All you need to set is PMUX value. TC specifically takes takes over. Although I'm not 100% sure with that new TC in SAM C, given that it also has direct inputs. So I would set it as an output.

I generally always explicitly set things as inputs or outputs even when I know that peripheral will take over, since it created a self-documenting code as well.

[Simon]

OK, just trying to make sure I do't create a conflict

[Simon]

16.8.3 clock generator

The divisor bits. Apparently gen 2-9 are 8 bits using bits 4:0, so which one is it? I assume a typo that should be 7:0 as 4 is below 7 and I can't see it being 5 bits.

[ataradov]

I think it should be DIV[7:0]. I'm pretty sure I used more than 5 bits.

[Lajon]

16.8.3 clock generator

The divisor bits. Apparently gen 2-9 are 8 bits using bits 4:0, so which one is it? I assume a typo that should be 7:0 as 4 is below 7 and I can't see it being 5 bits.

Yes 8 bits. This is corrected in the current revision of the data sheet (which is very recent, from January).
/Lars

[Simon]

Right I'll look up the latest copy. I have the PWM output working now. I had not enabled the clock in the main clock controller.

[Simon]

woah they have dropped over 100 pages. I wonder what changed.