EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: kgavionics on March 01, 2023, 04:33:57 pm
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Hello
AFAIK, the first step to configure external interrupts is to enable System configuration controller clock in the RCC APB2ENR register (bit 14), but to my surprise my external interrupts are working fine without enabling it!
Can someone shed some light on this subject please?
Thanks in advance
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STM32 SYSCFG is a weird thing. It just seems some kind of catch-all name under which some random registers were put in absence of better placement.
I'm not surprised at all that some of these registers seem to work without enabling the SYSCFG clock. It's probably something like the SYSCFG-located EXTI configuration registers being clocked from EXTI and not SYSCFG; i.e., maybe the registers are, after all, in one place, with rest of EXTI registers (EXTI_IMR etc.). If this is the case, it's beyond me why they are documented as being part of SYSCFG, but it would be typical ST. This is just a guess though.
But don't count on it working reliably, or with every device.
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Thank you for the clarification, Siwastaja!
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> my external interrupts
Let me guess: on PAx pins?
JW
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> my external interrupts
Let me guess: on PAx pins?
JW
yes!
Is there something special with GPIOA pins?
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They are selected by default in SYSCFG->EXTICRx, so you don't need to set anything in those registers.
If SYSCLK does not have clock, it means you can't set those registers, but not that they "don't work" - these in particular are pure memory-like registers which hold the value they've written, and internally they drive the EXTI input multiplexers. They hold zero after reset, and that corresponds to PAx pins in the EXTI multiplexers.
JW
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They are selected by default in SYSCFG->EXTICRx, so you don't need to set anything in those registers.
If SYSCLK does not have clock, it means you can't set those registers, but not that they "don't work" - these in particular are pure memory-like registers which hold the value they've written, and internally they drive the EXTI input multiplexers. They hold zero after reset, and that corresponds to PAx pins in the EXTI multiplexers.
JW
Thank you Wek for this nice explanation! That makes sense now!