I just got into SystemVerilog, and I made a simple led blinker that looks like this:
module CPLD(input CLK, input BTN, output LED);
reg [24:0] counter;
always @ (posedge CLK)
begin
counter <= counter+1;
if(BTN)
LED <= counter[23];
else
LED <= counter[22];
end
endmodule
When I compile this, Quartus II says it uses 25 logic elements of the CPLD.
However:When I replace all non-blocking assignments with blocking assignments, like this, I use 48 LE's, but it functions exactly the same:
module CPLD(input CLK, input BTN, output LED);
reg [24:0] counter;
always @ (posedge CLK)
begin
counter = counter+1;
if(BTN)
LED = counter[23];
else
LED = counter[22];
end
endmodule
I thought blocking and non-blocking assignments only affected simulation?
Here is the generated schematic for the non-blocking version that uses 25 LE's (I use the Quartus II RTL viewer):

And here is the schematic for the blocking version:

As you can see, the counter gets swapped with the adder, but functionality remains the same.
Please note that I am extremely new to all of this, so I hope some of you HDL guru's can enlighten me.

- Nick