How are you driving the LATCH pin?
At a guess you are idling high. When this pin is high, the latch is transparent, which means you are probably seeing the data as it is being shifted through.
You will want to keep LATCH low when shifting, then give just a brief high pulse to allow the newly shifted data through to the output drivers.
FPGA .. depends on the size of the matrix you want to drive, and how fast you want to refresh it. Small matrices can be done easily enough in software with timers and interrupts.