2023 Landscape of High-Performance Motor Control MCUs

[openyk]

Similar to Dave's recent MCU search, I also need to select a motor control MCU (sensored sinusoidal BLDC low-speed dual-encoder torque-sensing) and wanted to share my notes/thoughts in the pursuit of excellence. I'd appreciate any new ideas and suggestions.

Notable Features

High-Resolution PWM: 2ns previous-gen; 150-250ps current-gen

Multi-Core: typically main core1 for networking (ex. CAN-FD) and core2 for control algorithm and critical sensing; or lock-step.

ADC: 12-bit 3MSPS standard, 16-bit is leading-edge (reminds me of Siglent's 12-bit SDS-HD last year as a step up from traditional 8-bit)

Other Integrated: comparators, quadrature encoder interface, resolver interface, accelerators (algorithmic support), CRC

Options

Microchip dsPIC33CH series (2018, 16-bit, 512KB/48KB, 100MHz 90/100 MIPS dual-core, 250ps PWM, quadrature decoder) (AECQ-G0 150C operating models available) (power-efficient, thermally resilient, with several sizing options, though limited compute; classic rel-focused Microchip design style; reflects why NASA chose them for next-gen space HPC dev)

STM: STM32G4x4 (2019, 512KB/128K, M4-170MHz-213DMIPS, 184ps PWM, 5x 12-bit ADC 250ns)

TI: TMS320F280015x (2023, 32-bit, lockstep 120MHz, 256KB-ECC/36KB-ECC, 4x 150ps PWM, 2x 4Msps 12-bit ADC, 125C, FPU, TMU)

Renesas: RH850/U2B (2023?, 32MB CODE/512KB DATA/5MB RAM, 8x 400MHz cores, RISCV DFP-VE co-processor, eMMC, TSN-Ethernet, ASIL-D)

Renesas: RA6T2 (2021, 240MHz core, 950 coremark as of 2022-03-17, 156ps PWM resolution, 16-bit 160ns 6.25Msps latency dual ADC, 64KB RAM+ECC, 105C)

https://www.renesas.com/us/en/blogs/new-ra6t2-hybrid-16-bit-adc-improves-efficiency-and-accuracy-motor-control-systems

NXP: S32K39 (2023?, 32-bit, 4-6MB MEM, 800KB SRAM, lockstep M7-pair, split-lock M7-pair, dual co-processors, 160MHz DSP, CAN-FD/TSN-Ethernet, ASIL-D)

Questions

How relevant is memory/compute above 500KB/100MIPS for state-of-the-art algorithms (degree of improvement vs full optimization potential)? For example, NXP says they target 200kHz control loop designs.

What are the latest control design/algorithm advancements?

New MCUs seem to be targeting automotive electrification applications (big-featured traction inverter ECUs) and I don't need that many peripheral/functions (MFGs want to sell 1-2 per car, but my project needs 20+ per assembly), but aside from the extra size, cost, and power consumption, is there more I should be wary of when considering them for more compact applications?

[JPortici]

dsPIC33CH: I haven't really used them but i have some notes.

Slave Core:
Pro: has all the dedicated ADCs (high speed and very flexible triggering but fixed inputs, no channel scan.) and most high speed PWM
Con: May not have some other peripherals available that you may need. For example, generic ADC input, or more input captures. They are in the master core and you can only communicate data through the mailboxes.
Pro: Runs code from RAM, which means that it can achieve the slightly faster 100MIPS. It also means it doesn't have all the delays from flash wait, so delay on program memory access, delay on branches and gotos
Con: Image must reside in master flash (master has to load slave memory at boot) remember that when you size the part. A lot of flash will be eaten away by the slave core firmware.
Pro: Has some goodies such as dedicated context for each interrupt level (suppose you preload the coefficients and address offsets in the working registers, one per algorythm, and you algorythms is written in assembly. A context switch take a couple of cycles and can be performed automatically when entering/exiting interrupts.)
Con: Lacks FPU, Accumulator is 40bits but take 16bit operands.

[mkissin]

You probably need to supply more restrictions here.
I'm really only intimately familiar with the TI stuff as it's what I mainly use at work, but you've selected a (very new) entry level part there. Much higher performance parts would be the AM2634 or TMS320F28388D, depending on whether you like ARM or C2000 as a core architecture. Both of these are physically large chips though, and much more expensive.

[Siwastaja]

BLDC is easy-peasy. All specs I can see listed in your post seem overkill to me. Of course, if those parts are available and do not cost an arm (pun intended) and leg, then overkill doesn't matter, obviously. But just sayin'. Unless something very special is going on, I think very good motor performance can be had with a Cortex-M0 and something like STM32's Advanced Control Timers.

For research purposes, excess processing power helps because then you can try novel things out, some maybe impractically slow, without thinking about any optimizations; not even the low hanging fruits.