32F417 - any way to get baud rates below 1200?

[PCB.Wiz]

So although I know less about everything than everyone else, I think there is no 'wobble' and your bit times are consistent. I have a G0 doing 9600 baud from 16MHz, so I guess I could check it myself by hooking up the logic analyzer although I cannot get to the uart pins easily (although I can move the uart to other pins I can get to).

There will be some wobble in fractional UARTS, as any edge has to snap to a 42Mhz slot.
What the logic tries to do, is pick the best-fit 1/42M time tick, so the average can have better precision.
At low bauds like 9600, such ~24ns wobble will be lost in the dividers, to look for this effect you need to pick a much higher baud rate.

[peter-h]

After all this, is there any consensus on the actual hardware?

Is it possible that the two integers are just

- a clock prescaler
- a conventional UART divider

The CD4089 is just a sync counter with a selector on the outputs. It doesn't "multiply" the clock in any way.

" as any edge has to snap to a 42Mhz slot."

That's the clever bit I don't get.

[PCB.Wiz]

After all this, is there any consensus on the actual hardware?

Is it possible that the two integers are just

- a clock prescaler
- a conventional UART divider

Almost, you need to get the fractional decision in there somehow

The CD4089 is just a sync counter with a selector on the outputs. It doesn't "multiply" the clock in any way.

Yes, but it can give a varying density spread swallow pulse enable. Thus it gives a means to enable a /N or /(N+1) counter
By varying when that decision is applied, you can on average, get some average adder between +0 and +1 - ie a fraction

" as any edge has to snap to a 42Mhz slot."
That's the clever bit I don't get.

The edges have to be aligned to the clock, so the fractional part is an average over many bits.
None of the bits are actually of exactly the desired baud time, some are slower and some are faster, but any edge should (ideally) always be at the nearest (1/42M) time slot.

[amyk]

I don't think there's anything complex going on here; it's just a 16x or 8x fixed multiplier with a variable divider (the baudrate control register). It's not a coincidence that the oversampling is 16x (or 8x) and the "fractional" part of the register is 4 bits (or 3).

[cv007]

>I don't think there's anything complex going on here;

Most likely. For transmitting, they can simply count using the brr value and if over8 mode then they make bit3 'disappear' so the fractional part underflows/overflows from bit2 to bit4 doubling the speed. For receiving, they now have to sample probably 3 times somewhere in what they think is the middle of the bit time. The incoming clock drives everything (the internal bus clock).

The below takes the minimum value for the integer portion (which is 1) and uses both extremes of the fractional value. I'll assume everything above these numbers works out the same. The over8 mode somehow makes bit3 disappear, but don't know how- magic maybe.

====================================
default 16x mode
====================================

 |-1 bit time, 16 clocks-------|-|extra 1/16
|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|
 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
               |_|_|
               |-sample 3 starting here (#8)

brr = 0b10001 = 1 1/16
sample counter = 0b10001>>1 = 0b1000 = 8


 |-1 bit time, 16 clocks-------|---- extra 15/16-------------|
|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|
 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
               |_|_|--->     |_|_|
                             |-sample 3 starting here (#15)

brr = 0b11111 = 1 15/16
sample counter = 0b11111>>1 = 0b1111 = 15


====================================
over8 mode - make bit3 disappear
====================================

 |-1 bit time  |-|--extra 1/8
|x|x|x|x|x|x|x|x|X|
 1 2 3 4 5 6 7 8 9
       |_|_|
       |-sample 3 starting here (#4)

brr = 0b1_001 = 1 1/8
sample counter = 0b1_001>>1 = 0b100 = 4


 |-1 bit time--|-|-extra 7/8-|
|x|x|x|x|x|x|x|x|x|x|x|x|x|x|x|
 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
       |_|_|>|_|_|
             |-sample 3 starting here (#7)

brr = 0b1_111 = 1 7/8
sample counter = 0b1_111>>1 = 0b111 = 7

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[PCB.Wiz]

I don't think there's anything complex going on here; it's just a 16x or 8x fixed multiplier with a variable divider

That's easy to say, but is actually complex in silicon. Multipliers are very hard to do, especially over wide clock ranges.

The simplest solutions are entirely digital.

The simplest digital solution I can see is a /N or N+1, which you implement with an optional single FF delay on the reload, and that decision comes from a Rate Multiplier fed from the fractional bit field.
The outcome is edges that jitter, by 1 sysclk, but  the average across a whole data byte is less than 1 sysclk.

[abyrvalg]

Also note that fractional wobbling applies to x16 (x8) sampling clock. The bit duration still can be expressed as an integer number of source clock pulses by design. So in the worst case we have wobbling sampling points within a stable bit, who cares? Majority encoder will hide it.

[peter-h]

Turns out the proposed solution - dropping PCLK2 to the lowest figure of 10.5MHz - is a problem if you want to use ethernet. Some undocumented hardware bug:

https://www.eevblog.com/forum/microcontrollers/stm32f417-any-reason-why-a-min-pclk2-speed-is-required-for-ethernet-to-work/msg3571352/#msg3571352

EDIT: the latest reference manual, Feb 2021, modifies some of the supported baud rate tables, and confirms the above conclusion i.e. at 42MHz PCLKx, the achievable rates are 644 baud (my own measurement, and implied by their "1200" figure) to 1843200 baud (their figure, which correlates with me measuring 2x that as max possible with an 84MHz PCLK2).

Update: actual tests with a 42MHz PCLK show a range of 642 baud to over 2.7mbps.

The error goes somewhat above 1% at the top end. At 1843200 it is 0.7%. At 115200 it is 0.17%. At 38400 it is 0.02%.