Electronics > Microcontrollers

32F417 SPI running at one third the speed it should

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Siwastaja:

--- Quote from: peter-h on February 03, 2022, 03:57:39 pm ---Hmmm... I have NRST unconnected too. Didn't put a cap on it because the debugger drives it. But presumably 10nF should be safe?

Given it has a ~40k pullup, one would need a fairly powerful radiated spike to pull it down for long enough. This is the data sheet, showing 100nF

--- End quote ---

The very point of my post was, the reference manual, where this information does not belong at all, gives completely different rationale for the capacitor: it is Just Needed. They don't give the exact reason, but at least H743 with external Vcore* fails to start without the capacitor, and it has nothing to do with EMI or radiated anything, the test environment was quiet and I probed that pin to verify clean signal - rising fast, though, as expected without the cap. The CPU clearly needs the slow ramp on the pin, lengthening the internally generated power-on reset pulse.

*) I'm mentioning this because it could be important, even though the thing should boot with internal LDO regardless, but maybe there is some weird power sequencing thing going on. In any case, the capacitor is needed per the reference manual, and not needed per the datasheet. That's the point. You have to read all the documentation carefully.

It's actually quite classical to somehow f*** up the internal reset circuitry. Early AVR devices were known to have issues to the point people designing in external power-on-reset driver ICs. Later AVRs supposedly fixed it, but still required smaller external pull-up and some official programmers denied working if they did not detect the correct amount of resistance.

harerod:
The attached STM32H743 excerpt from the datasheet might shed some light on  Siwastaja's NRST mystery: "6.3.16 NRST pin characteristics"
Not only does it give the "Figure 23. Recommended NRST pin protection", it also gives the "Table 65. NRST pin characteristics", which include timings. I would just assume that a pin without cappa and excellent layout (e.g. no pin loading at all) might actually violate these requirements.
However - peter-h wrangles the venerable STM32F417. The NRST is described in the datasheet under "NRST pin characteristics". Minor differences, only.

AndyC_772:

--- Quote from: Siwastaja on February 03, 2022, 05:51:31 pm ---The very point of my post was, the reference manual, where this information does not belong at all, gives completely different rationale for the capacitor: it is Just Needed. They don't give the exact reason, but at least H743 with external Vcore* fails to start without the capacitor

--- End quote ---

Thank you for sharing this observation, you've probably just saved me hours of head scratching.

I've just completed a prototype using the STM32H723, my first design with an H7 device. Like the part you're using, there's nothing about needing a capacitor in the data sheet, but it's prescribed in the full Reference Manual. Fortunately I can solder one easily across the back of the debug connector, where NRST and GND appear adjacent to each other. Glad I went for the full size 0.1" header this time...!

Fig. 43 (page 309) shows a simple block diagram of the reset circuit, including a 20us pulse generator which drives the NRST pin. This block has inputs 'pwr_bor_rst' and 'pwr_por_rst', which imply that the device should generate its own nice, clean 20us reset pulse following power-up or a brown-out.

I wonder whether perhaps this pulse generator simply doesn't work, or at least, doesn't work properly at power-up?

Siwastaja:

--- Quote from: AndyC_772 on February 03, 2022, 06:22:18 pm ---I wonder whether perhaps this pulse generator simply doesn't work, or at least, doesn't work properly at power-up?

--- End quote ---

My take is, it generates a pulse that is too short, or does it too early. This pulse is exposed on the pin, so adding C creates a simple RC delay with the internal pull-up.

Protection against noise and ESD are additional benefits, but clearly not the actual reason why it's needed.

I also scoped my supplies and they were increasing nicely and monotonically. Internal POR circuit should have no difficulties...

Obviously nobody will follow that "recommended circuit" of the datasheet, because it includes a pushbutton, and 99% of the products do not use reset buttons, except devboards. And in that "recommendation", the capacitor is grouped with the mechanical switch, clearly indicating they belong together, making people easily ignore the capacitor.

peter-h:

--- Quote --- H743 with external Vcore* fails to start without the capacitor,
--- End quote ---

It won't be due to the slower risetime enabling a start. It will be because it starts up, the HS oscillator starts up, and then it samples NRST, and if it is HIGH then it bombs. So the cap is needed for a delay. Or it may just need a delay on NRST after VCC rises.

I am not surprised they screwed this up. NRST will have a messy rise; all you need is a non monotonic VCC rise and the hardware will see a "pulse" on NRST.

Historically a reset without a "supervisor" has simply not worked. I have for many years used the Seiko S808
https://eu.mouser.com/ProductDetail/ABLIC/S-80825CNMC-B8KT2G?qs=1uru1TqDsKB%2FV9OyZye9RA%3D%3D
with Atmel 90S1200 AVR and other chips. For the Hitachi H8/3xx I have used the Maxim MAX706 but have just designed out those scammers and put in the ST version
https://eu.mouser.com/ProductDetail/STMicroelectronics/STM706M6F?qs=QRsLLuHQazBglYFCH0NTIg%3D%3D

I am just about to populate 10 boards and will fit the 10nF on all, then change the design to add this.

The pushbutton is optional, but it is dumb because it will bounce around. The 417 data sheet says it will reject <100ns pulses and will accept >300ns pulses. A switch will not do either :) If I really had a button I would put in a schmitt trigger to feed NRST (and made the cap TC a lot longer; say 100ms).

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