Just a cute byproduct of today's development work:
Oh, one thing I forgot to adjust, the samples are in reverse order. Just mentally tack on a minus to the times then.
They don't specify the sampling aperture in the datasheet (only the sample period, a couple clocks or more), but it does look to be comparable to the ADC clock. There is some evident rounding at the, whatever you want to call it, the rising zero crossing flat there (at ~12.8us), but hard to say how that translates into bandwidth.
Why the dumbass waveform? First thing I tried, just happy that it works.
The flat is dead time between triggers; it's just a triangle function triggered by the master timer (Ch2) (which also triggers the ADC, after a programmable delay). A square wave isn't actually much crisper, due to filtering in the circuit. Well, geh, let me bump that off and see what it does... ah yeah, that's a bit better isn't it. Seems to stabilize within about 4 clocks [of 24MHz], or ~170ns. So, presumably, analog bandwidth on the order of 3MHz. Which seems pretty typical, given the max sample rate is 130kSps.
Note that, although the ADC is clocked from a prescaler, the prescaler is reset on start, so it's synchronous only to CLK_PER (24MHz here), and I have full [24MHz] granularity on the equivalent time sampling here. Put another way, that's as if my TDS460 (actually 100MSps and 350MHz) said 50kSps, 3MHz BW and 24MSps effective.
Tim
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