Hello!
as I have mentioned in another thread about (still and again just other) FPGA minimalistic board, I like also to design small PLD kits. One of my boards includes Altera's EPM3064, a small 44pin CPLD. As a clock source, I decided to use a 32.768kHz crystal to provide both 2048Hz and 2Hz clocks, by using a "classic 4060" chip. But it doesn't work, I don't know why. That's the only thing preventing me from publishing the design for anyone interested.
Can you please help me to solve the mystery, why it doesn't oscillate?
As the whole board is powered from 3V3 supply, I have decided to use 74HC4060 version of the IC. The schematic diagram is below.
I have tried 7pF and 12pF Cload crystals, tried changing the loading caps to whatever crazy values up some hundred puff, tried changing the feedback resistor from 100k up to 1M. (The series resistor R41 is now shorted) Nothing helped. And yea, the IC is not blown. Sticking a finger on its input makes it count.
Do you have any ideas, what I have done wrong or how to design it properly, so it will oscillate?
Btw, have also checked if there is enough gain margin, and as I remember there was a great margin.
Thank you for help!
Yan