512 Megabyte sdram for stm32

[seyedsaeed]

Hi
Please, introduce 512 Megabyte SDRAM for stm32h755

[langwadt]

I think the biggest SDRAM is 512Mbit, you'll need 8 chips or an old RAM stick

[Georgy.Moshkin]

Have you looked into IoT RAM or PSRAM? It's not what are you looking for, but maybe worth considering. There are 512 Megabyte options in a small low pin count packages by different manufacturers, options are limited by low voltage logic levels, but there are 3V too.
https://www.st.com/en/partner-products-and-services/iot-ram-spi-qspi-psram.html

[hans]

That ST part can't even map or control 512MB of SDRAM, I think:

13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit
(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)

2^13 * 2^11 = 16M addressing capability. At 32-bit bus width thats 64MByte per bank.
You'll need to connect 4 banks to address 256MByte.

But routing a 32-bit data + 13-bit address bus to 4 SDRAM packages doesn't sound that fun, but should be possible.
The old 144 or 168-pin SDRAM standard use 8 banks and thus a 8x8-bit = 64-bit data bus, so you'll lose half the memory capacity of those sticks.
The 72-pin SDRAM DIMMs have a 32-bit bus, but I haven't seen those in high capacity.

[seyedsaeed]

FMC memory Banks

SDRAM controller

 I discover only one sdram with name MT46H64M32LF

[hans]

That's a DDR module. SDR is different.

SDRAM is the technology of the data cell, as opposed to SRAM cells.

SDR and DDR transfers is about the memory bus being able to clock 1 or 2 transactions per clock period, respectively.

If you want to run DDR memory on a STM32, look into sidestepping to e.g. a H725 which supports OctoSPI and Hyperbus chips. But I don't think higher capacity chips exist of those.

[seyedsaeed]

If you want to run DDR memory on a STM32, look into sidestepping to e.g. a H725 which supports OctoSPI and Hyperbus chips. But I don't think higher capacity chips exist of those.

I need stm32H755 and 512 MB RAM.
If you know, please tell me the name of a RAM.
Datasheet: Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories.

[SiliconWizard]

What are you going to do with 512MiB of RAM and a MCU, if we can ask?

[nctnico]

I discover only one sdram with name MT46H64M32LF

It looks like the controller has two SDRAM memory banks of 256MByte each (64Mbit x 32) which makes 512MB in total. You'll need 4Gbit of memory while the largest SDRAM chips available seem to be 512Mbit so you'll need 8 chips. The ISSI IS42S16320F-7TL could be an option but you'll need to put 4 chips in parallel to the same data bus and 8 chips in parallel to the same address but. Not an easy task to route especially since SDRAM has rather strict timing requirements. DDR memory has seperate clocks to synchronise data transfers and make routing easier but SDRAM does not.

[radiolistener]

What are you going to do with 512MiB of RAM and a MCU, if we can ask?

it depends on how to write code, it is possible to write hello world which can allocate 512 GB 

[seyedsaeed]

What are you going to do with 512MiB of RAM and a MCU, if we can ask?

It is for an important research work.

[radiolistener]

If you really needs 512 MB RAM, I think MCU is a bad choice for that. I would suggest to see something like raspberry pi, odroid-m1 or something like that

[seyedsaeed]

If you really needs 512 MB RAM, I think MCU is a bad choice for that. I would suggest to see something like raspberry pi, odroid-m1 or something like that

Yes really, but it has to be done with the microcontroller, not anything else, not even FPGA or...

[Georgy.Moshkin]

1. In one of my stm32 projects I had pretty big 3d arrays. They could not fit in the ram, so I was using binary space partitioning algorithm. It was kind of compression algorithm for storing only nonzero values. I was not knowledgeable enough at that time, and used Delphi to write proof of concept and then ported it to C and tested on stm32f446. Although access speed was slow, it was working. With my todays knowledge I can do much better, especially on H7. I can use TCM memory for time critical portions of code and data, or use cache, etc. So there is an option to compress your data, it may be applied if compression performance is acceptable.

2. Use second MCU to emulate large memory. Or do data exchange through PSSI interface. Second MCU can read/write data to few psram low-pin-count chips, or even swap to sdcard. Internal memory of second chip can be used as cache and prefetch buffer. May work pretty fast if there are no random reads/writes.

Both approaches have many different wasys to implement, there are no performance miracles, but I think in some rare cases results may be very interesting.

[seyedsaeed]

Thanks everyone, but I only need 512MegaByte of RAM.
And not anything else
It is very important and vital that this is done, and in the next phase, which must be done with FPGA, much larger RAMs are needed.

[hans]

Well solutions have been given to you. Get 2 groups of 4x 512Mbit SDRAM chips with 8-bit data bus, and find someone that will torture themselves to route the PCB for it, if at all possible. If you have searched extensively for larger SDRAM chips and found 0 results, then its unlikely a 4Gbit SDR SDRAM chip exists, off the shelf, in 1 package, because there is no large scale demand for it. But it looks like you're pretty fixed to the parts chosen, so that also means the answer is pretty fixed.

Higher density memory chips have moved to DDR, DDR2 etc. buses which allow for reasonable access times to the whole memory array. At 512MB and a 100MHz SDR 32-bit bus (if you happen to get a working PCB layout for that), you're looking at 1.2+ seconds to do a full read of the array, neglecting access times, maximum burst sizes, memory refresh cycles and protocol/addressing overhead, which will probably increase it to 1.5 seconds or so. This is the reason for the "why?". I think most applications wanting 512MB would also want/need the memory bandwidth to support it.

If all you need is capacity, you could look in other ways of emulation. Multiple PSRAM chips that work over QuadSPI (note that ST's memory-mapped QuadSPI controller is meant for read-only modes only  IIRC, e.g. FLASH). Or crazy idea: a 1TB SD card and trust the wear leveling. Even the most trash quality FLASH with only 300P/E cycles would last almost 1yr when it's continuously written at 12.5MB/s (SDIO bus 50MHz).

[nctnico]

A better option would be to use a SoC which has a DDR memory interface. You don't need to run Linux on it in case the task isn't demanding. U-boot has all the features you need to create a lightweight platform.

[seyedsaeed]

Thank you very much to everyone.
I just realized.
I have to use 8 pieces of RAM in parallel.

[Siwastaja]

Get 2 groups of 4x 512Mbit SDRAM chips with 8-bit data bus, and find someone that will torture themselves to route the PCB for it, if at all possible.

Why do you think it's torture or difficult? Usual job for a PCB designer, multi-RAM-chip modules have always been commonplace and somebody designed them. Given this project is super important super secret scientific instrument, they should be able to afford as many PCB layers as required, not to mention lasered microvias, buried, blind vias etc., which make the layout work even easier.