DiTBho kindly asked me in PM how did I come to the conclusion that:
Fine at 1 MHz, from a quick check of the timing diagram. Definitely not at 2 MHz.
Hoping that the answer might be useful to someone else, I'll put it here, instead of a PM to them.
First, I got the timing diagram and values for the non multiplexed bus of the F1 from
here, Appendix A (see Picture1 and 2 attachment).
Then I got the same for the EPROMS, see Picture 3 - this is for a 350 ns access time 2716, which is more conservative wrt the OP EPROM (300 ns).
Last I checked the 6840 timing, Picture 4.
Now I have everything I need.
We need to make timing requirements in Picture2 are fulfilled.
For reads from the FW EPROM to succeed, I look at the second falling edge of E and work backwards.
Setup time (17) is 30 ns at 2 MHz, let's be conservative and use 40 ns (as it seems to decrease when raising the frequency).
Hold time (18), 0 ns for all clock frequencies, let's go with that (i.e. no need to check it!)-
Now, since I had suggested to qualify the /OE signal with E & R/W, i.e. use the already available RD and as this was a quick check I'll ignore the handful of ns of an HC gate), /OE will become valid (low) when E rises (R/W from the MCU is stable long before).
I look in Picture3 to t
GLQV, time from /OE low to data out: 120 ns: with 500 ns half cycle, we have a margin of:
500 - 120 - 40 = 340 ns, no issue here.
Then I checked the time it takes the 2764 to provide a stable output, t
ELQV: 350 ns.
The time needed for the 2732 to give a valid /CS to the 2764, is of course the same.
Going backwards from the E falling edge, we need to sum:
40 ns setup time
350 ns 2764 access time from /OE
350 ns 2732 access time (since its /OE and /CS are always active, I use t
AVQV in Picture3
165 ns Address Delay Time (11 in Picture 1 and 2), 1/8 cycle time + 40 ns
-------
905 ns
As this is less than our 1000 ns cycle time (and we have about 100 ns margin to add, as I used 350 ns instead of 300), I foresee no issue.
The same exercise, mutatis mutandis, can be applied to the 6840 - similar results.
So OK for 1 MHz E clock.
Not so much for a 2 MHz one, the first check will still be OK, but the second one gives:
30 ns setup time at 2 MHz
300 ns 2764 access time from /OE
300 ns 2732 access time (since its /OE and /CS are always active, I use t
AVQV in Picture3
103 ns Address Delay Time (11 in Picture 1 and 2), 1/8 cycle time + 40 ns
-------
733 ns
50% greater than our cycle time, so no go.