Note that I only used a 68HC11A8, and many years ago.
As you suspect, the quartz/oscillator frequency is internally divided to generate an 4 phase clock for internal needs (e.g. fetch decode execute etc. - though I don't have details).
One of these phases is brought out as E.
So, with a 1 MHz external clock the actual system/memory clock (E) is 250 kHz.
Depending on your needs, this might be what you wanted or not; still, it's E that must be used to e.g. gate memory control signals.
Unless you need it for debugging and trouble shooting, I would not set the Internal Read Visibility bit: in Expanded mode there might be bus contentions.
What the bit does is driving data read from registers or internal addresses on the data bus - useful with a logic analyser, but otherwise not needed.
Having or not an active watchdog is your design choice: if active, it must be periodically kicked by the FW; since you are asking, I suppose you don't need it and would leave it disabled.