Author Topic: 8$ iCE40 developer board..  (Read 29574 times)

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Offline tiltit

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Re: 8$ iCE40 developer board..
« Reply #125 on: February 18, 2018, 02:33:46 pm »
I have just received the upduino V2. It took about a week and a half to get to Germany. When I first plugged it in it wasn't drawing any current, then I noticed that the micro usb connector wasn't properly soldered on. Once that was fixed I got it working with the open source yosys and icestorm toolchain. I am now trying to lean verilog and how to make use the thing. I have still no idea what I can use it for but I find it interesting none the less. Overall I think it's quite good, it permits me to experiment with an fpga without having to spend a lot money for something that may or may not be useful to me. In any case it is interesting to see how different it is from writing a program for a microcontroller.
Does anyone know if there is a simple cpu core that would fit onto it? I understand that 5K Lut is quite small.
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #126 on: February 18, 2018, 03:09:53 pm »
FYI - you may go to OpenCores, Processors tab, and you get a list of various verilog/vhdl CPUs. A CPU which fits into ~1500 LUTs of Xilinx may fit in UPduino. The only issue could be the 15kB of internal bram only (which can be loaded out of bitstream upon boot), and the fact it cannot be inferred easily (has to be done manually). You have got 128kBytes of single port ram which could be used as well (but it cannot be loaded off the bitstream). You may attach an external sram, the limit is the number of available i/o pins. If you are keen on Forth the J1a CPU fits nice.
« Last Edit: February 18, 2018, 03:14:34 pm by imo »
 

Offline mark03

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Re: 8$ iCE40 developer board..
« Reply #127 on: February 18, 2018, 06:40:01 pm »
I bookmarked this a while back:

https://github.com/cliffordwolf/picorv32

I'm sure there are plenty of small cores to choose from, but this is RISC V which IMO makes it compelling quite apart from its capabilities/attributes.  (I think RISC V is likely to become more important in the future == good to learn.)
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #128 on: February 20, 2018, 06:57:00 pm »
I've got the v2 and it works fine  ;)
Tried with Diamond programmer.
Btw, the mail sorting machines are not v2 friendly - it took me half an hour to get the tiny usb socket work (deformed by the machines).
« Last Edit: February 20, 2018, 06:59:05 pm by imo »
 

Offline Cerebus

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Re: 8$ iCE40 developer board..
« Reply #129 on: February 23, 2018, 11:59:56 am »
It's increasingly looking like the issues I'm having with the iCE40 board I made are due to my remarkably poor decision to enable VCC/VCCPLL manually *after* powering the IOBanks. I removed all other SPI devices from the board, and it still won't assert VCCPLL.

From the data sheet:

Quote from: iCE40 UltraPlusTM Family Data Sheet
4.5. Power-up Supply Sequence
It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay between the power supplies, however, there is a requirement for each supply to reach a level of 0.5 V, or higher, before any subsequent power supplies in the sequence are applied.
1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to TN1252, iCE40 Hardware Checklist.
2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have reached as level of 0.5 V or higher.
3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1) have reached a level of 0.5 V or higher.
4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down sequence required. However, when partial power supplies are powered down, it is required the above sequence to be followed when these supplies are re-powered up again.


Note the usual Lattice data sheet clarity! Oh Boy, do they need to hire some better tech writers.

I don't think that it's an accident that the required 0.5V is a diode drop at low current. That is, I suspect it represents substrate diodes (isolation tubs, whatever) between the subsystems which are required to be held reverse biased at all times.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #130 on: February 23, 2018, 05:57:59 pm »
I do not think the UP5k dev boards I've seen (and I've got ie UPduino v1, v2) care much about the sequence, and they simply work..
 

Offline Cerebus

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Re: 8$ iCE40 developer board..
« Reply #131 on: February 23, 2018, 06:42:51 pm »
I think you're OK as long as you don't have the bias the wrong way around - so bringing up all the rails at the same slope is OK, bringing up VCC and VCCPLL after the IO rails isn't OK.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline daveshah

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Re: 8$ iCE40 developer board..
« Reply #132 on: February 23, 2018, 07:04:57 pm »
I think most of the cheap boards derive 1.2V from 3.3V using an LDO (usually itself derived from 5V with another LDO), so 3.3V VccIO will be brought up first, but presumably the difference and/or time period isn't high enough to cause a practical problem...
 

Offline Cerebus

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Re: 8$ iCE40 developer board..
« Reply #133 on: February 23, 2018, 07:42:25 pm »
Really need some graphs here but I can't be bothered. If you derive the 1.2V from 3.3V then they both tend to ramp up to the same voltage at the same time (i.e they both have the same dv/dt and perhaps a small offset) until the higher supply overtakes the lower supply at 95-100% of the lower supplies final value. Separately derived supplies may have different slopes and often tend to hit the same proportion of their final voltage at the same time.

The iCE40 is very forgiving in terms of power supply sequencing; check the specs of some other FPGAs and you can find requirements that are hard enough to meet that specific power supply chips have been developed to go with them. I think cleaningOut above just managed to find the one power sequencing order that the iCE40 chips won't tolerate, which appears to be bringing VCCPLL up late.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #134 on: February 23, 2018, 07:55:48 pm »
This is the most probable power-up sequence with UPduino v2:

« Last Edit: February 23, 2018, 08:33:35 pm by imo »
 

Offline aventuri

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Lattice Radiant: new IDE for iCE40 UltraPlus like Upduino's UP5K
« Reply #135 on: February 27, 2018, 09:44:15 am »
hi,

just a note about a new software called Lattice Radiant that has been released.

it should target precisely the Upduino FPGA iCE40 UltraPlus UP5K.. it should run both on indows and Linux. But a quick shot to install it on Debian turned me down, because it says "Fedora/RedHat" only.. let's see in next days..

I'm really wondering why they departed from IceCube2 with a new IDE specifically for UltraPlus..  anyone hints?

bye

andrea
 

Offline ale500

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Re: 8$ iCE40 developer board..
« Reply #136 on: February 27, 2018, 11:58:28 am »
Quote
just a note about a new software called Lattice Radiant that has been released.

Just when I was hoping they would integrate them into Diamond...

From the demo video it looks like icecube with a new GUI..
 

Offline daveshah

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Re: 8$ iCE40 developer board..
« Reply #137 on: February 27, 2018, 12:00:30 pm »
Just when I was hoping they would integrate them into Diamond...

From the demo video it looks like icecube with a new GUI..

As far as I can see, it's actually much closer to Diamond with a new GUI (and limited device support) under the hood. Also, they renamed all the primitives - mostly removing the "SB_" prefix, the last remaining trace of the iCE parts' SliconBlue heritage.
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #138 on: February 27, 2018, 09:44:09 pm »
Radiant: It is not only the SB_ prefix..  >:(
There is a migration document, all stuff has been renamed somehow. They mention "Radiant IP Catalog " I cannot find. You cannot take the IceCube2 verilog, remove SB_ and run under Radiant, no way..
I've installed it under Win7, the license var name the same as the of Diamond :(
Much better editor  ;) and the Radiant programmer is integrated as well (the same as the Diamond's stand alone one)..
« Last Edit: February 27, 2018, 09:56:08 pm by imo »
 

Offline daveshah

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Re: 8$ iCE40 developer board..
« Reply #139 on: February 27, 2018, 09:52:46 pm »
There isn't a published ip catalog yet, but you can work a lot out from the provided simulation and cell libraries.

It seems as well as the name changes the format of the parameters also changes, from being a Verilog number parameter to a numeric literal inside a string.
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #140 on: February 27, 2018, 10:03:02 pm »
Radiant: not compatible with IceStorm anymore..  >:(
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #141 on: March 06, 2018, 08:44:42 am »
Radiant: Reveal analyzer does recognize the FT232H (an external cheapo board).
Code: [Select]
INFO - cable[0]=FTUSB-0,USB2,Single RS232-HS Location 0000Mind you have to enable the reveal's cableserver in your firewall, however.. :)
 

Offline ale500

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Re: 8$ iCE40 developer board..
« Reply #142 on: March 10, 2018, 04:48:57 am »
The UPDuino board has a 4 MByte Flash device, but the configuration needs like 75 kBytes... Does anybody know how to pre-program some use data ?
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #143 on: March 10, 2018, 12:43:21 pm »
The bitstream is first 104156 bytes. You can access (read/write) data in the 4MB bitstream SPI flash from verilog/vhdl. The UP5k's "special" SPI flash pins work as standard io pins after the UP5k boots. Pre-programming the SPI flash with user data has to be done via your programmer (any SPI flash programmer works).

PS: for example there is the icestorm's  multi tool - it could be easily modified to incorporate any user data into the bitstream, I guess..  :)
« Last Edit: March 10, 2018, 01:09:37 pm by imo »
 

Offline s4

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ships same day in Germany
« Reply #144 on: January 09, 2019, 10:53:01 am »
mouser.de ships it same day for €40 with a nice camera+microphone board. Also Lattice has that same double package.  :-+
 

Offline s4

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J1 Forth soft-CPU
« Reply #145 on: January 09, 2019, 10:55:07 am »
did anyone manage to run the famous  J1  Forth  soft-CPU on it ?

on the UPduino  or the NAND-Land  GO board ?  both have same FPGA by LAttice
 

Offline s4

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Re: 8$ iCE40 developer board..
« Reply #146 on: January 09, 2019, 01:24:42 pm »

this guy seems to be #1 on the Forth MCU front:   :clap: http://excamera.com/sphinx/article-j1a-swapforth.html  :horse:
 

Offline imo

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Re: 8$ iCE40 developer board..
« Reply #147 on: January 09, 2019, 01:31:44 pm »
did anyone manage to run the famous  J1  Forth  soft-CPU on it ?

on the UPduino  or the NAND-Land  GO board ?  both have same FPGA by LAttice

Here you are - with improved J1a and the famous Mecrisp Forth:

https://github.com/igor-m/UPduino-Mecrisp-Ice-15kB

Ready to build with IceStorm, IceCube, Radiant..
« Last Edit: January 09, 2019, 01:42:45 pm by imo »
 


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