1802  RCA  ? Most instructions take 16 clocks (6.4μs), some, 24 (9.6μs). 2.5MHz @ 5V. 
8080  Intel  ? (still waiting for information) 
8088  Intel  10 bus cycles or 40 clocks(?) (B)+(C) (still waiting for further information) 
8086  Intel  WDC says 182 clocks max total latency. * * * * * (still waiting for information) 
Z8  Zilog  IRET (E) takes 16 execution cycles. I don't know how many clock cycles per execution cycle. 8MHz? 
Z80  Zilog  1119 clocks (B)+(C) depending on mode, or 2.754.75μs @ 4MHz. RETI (E) is 14 clocks, or 3.5μs @ 4MHz. 
Z8000  Zilog  IRET (E) takes 13 cycles in nonsegmented mode, and 16 in segmented mode. I don't know if that's instruction cycles or clock cycles. 
8048  Intel  (?) return (E) is 2.7μs @ 11MHz 
8051  Dallas  1.5μs @ 33MHz (52 clocks) latency 
8051  Intel  1.8μs (C) min @ 20MHz. 5.4μs (A)+(C) max total latency @ 20MHz. (39μs @ 12MHz.) Interrupt sequence (C) and return (E) take 4.6μs @ 20MHz ST 
80C51XA  Philips  2.25μs for interrupt+return (C)+(E) @ 20MHz. ST Instructions 224 cy, or 0.11.2μs. Avg 56 cy, or around 0.27μs. 
KS88  Samsung  3μs for interrupt+return (C)+(E) @ 8MHz ST Instructions 628 cy, or 0.752.5μs. Avg 11 cy, or 1.38μs. 
78K0  NEC  4.3μs for interrupt+return (C)+(E) @ 10MHz ST Instructions 450 cy, or 0.45.0μs. Avg 15 cy, or 1.5μs. 
COP8  National  70 clocks (7 instruction cycles). RETI (E) is 50 clocks (5 instruction cycles). (7μs & 5μs @ 10MHz) 
μPD78C05  NEC  RETI (E) takes 13 or 15 clocks (2.08 or 2.4μs at 6.25MHz) 
μPD70008/A  NEC  sequence (C) takes 13 or 19 clocks. Return (E) takes 14 clocks. Instructions take 423 clocks each. 6MHz in '87 book. 
V20  NEC  RETI (E) takes 39 clocks or 3.9μs @ 10MHz in '87 book. Instruction set is a superset of that of 8086/8088. 
V25  NEC  ? (still waiting for information) 
68000  Motorola  46 clocks or 2.875μs minimum @ 16MHz (B)+(C)?. Has a very complex interrupt system. 
6800  Motorola  (C)=13 clocks, including pushing the index register and both accumulators. RTI (E) takes 10 clocks. 2MHz. 
6809  Motorola  (C)=19 clocks. Stacks all registers. RTI (E) 15 clocks. 2MHz (8MHz/4). FIRQRTI take 10 & 6 clocks, & work more like 6502 IRQRTI. 
68HC05  Motorola  16 clocks typ (8μs @ 2MHz) 
68HC08  Motorola  Instructions 19 cy, or 0.1251.125μs. Avg 45 cy, or around 0.55μs. 
68HC11  Motorola  (C)=14 clocks. RTI (E)=12 clocks. Total for interrupt+return=8.75μs @ 4MHz (16MHz/4). ST Instructions 241 cy, or 0.510.25μs. Avg 67 cy, or around 1.6μs. 
68HC12  Motorola  2.63μs for interrupt+return (C)+(E) @ 8MHz. ST Instructions 113 cy, or 0.1251.625μs. Avg 34 cy, or 0.45μs. 
68HC16  Motorola  2.25μs for interrupt+return (C)+(E) @ 16MHz. ST Instructions 238 cy, or 0.1252.375μs. Avg 67 cy, or around 0.4μs.

PIC16  Microchip  (C)=8 clocks (2 instruction cycles), and RETFIE (E) is also 8 clocks; but this doesn't even include saving and restoring the status register. That's an extra, rather mickeymouse operation. 20MHz Most instructions 4 cy, or 0.2μs. 
TMS370  TI  15 cycles (3μs) min (C), 78 (15.6μs) max (A)+(C), and a cycle is 4 clocks (200ns min)! 20MHz. RTI (E) is 12 cy (48 clocks or 2.4μs). 
TMS7000  TI  (C)=19 cycles min (17 if from idle status) 5MHz, 400ns min cycle time (IOW, interrupt sequence is 7.6μs min, 6.8 from idle.) RETI (E) is 9 cycles, or 3.6μs @ 5MHz. 
ST6  STM  78 clocks min, or 9.75μs @ 8MHz to fetch interrupt vector. More to reach first ISR instruction. RETI is 26 clocks, or 3.25μs. 
ST7  STM  3μs for interrupt+return @ 8MHz. ST Instructions 212 cy, or 0.251.5μs. Avg 45 cy, or around 0.55μs. 
ST9  STM  External IRQ best case: 1.08μs @ 24MHz. NMI best case: 0.92μs. internal interrupts best case: 1.04μs. 2.25μs @ 24MHz for interrupt and return ST Instructions 638 instruction cy, or 0.53.67μs. Avg 17 cy, or around 1.4μs. 
ST9+  STM  1.84μs @ 25MHz for interrupt and return, ST Instructions 226 instruction cy, or 0.161.04μs. Avg 11 cy, or around 0.9μs 
H8/300  Hitachi  8/16bit: 2.1μs @ 10MHz for interrupt and return ST Instructions 224 cy, or 0.23.4μs. Avg 56 cy, or around 0.55μs.

M16C M30218  Mitsubishi Renesas  18 cy min (C), or 1.125μs @ 16MHz w/ 16bit data bus. 50 cy max (A)+(C). REIT is 6 cy, or 0.375μs. Dual register sets like the Z80. Max instruction length 30 cy. 
CIP51  Silicon Labs Cygnal  μC p/n C8051F2xx) total latency 518 cy or 0.20.72μs @ 25MHz. RETI takes 5 cy, or 0.2μs. This is the only one I have data on here that gives the 6502 below any competition. 
65C02  WDC  Normal latency (C) 7 clocks (0.35μs) min, 14 clocks (0.7μs) max (A)+(C). RTI 6 cy (0.3μs). 20MHz. Instructions 27 cy, or 0.10.35μs. Avg 4 cy, or 0.2μs. Special case: IRQ from WAIt instrucion with interruptdisable bit I set: no more than 1 cy (0.05μs!) 