9S08PA16 - how to reset timer?

[Circlotron]

On the HC08 there was a timer status & control register with bits for overflow, reset, stop and clock divider amongst others. With this 9S08 THING  the register has an overflow bit but the reset bit is who knows where... 12.3.3 Status and Control (FTMx_SC) gives not enough information. The advertising blurb says these things are backward compatible with legacy HC08 code. What a load of rubbish. 

It does say "Writing any value to COUNT_H or COUNT_L updates the FTM counter with its initial
16-bit value (contained in the Counter Initial Value registers) and resets the read
coherency mechanism, regardless of the data involved in the write."

Is this the right way to reset this counter?

[jaromir]

FTM is quite complex peripheral, most suitable to generate all sorts of PWM waveforms. Is this what you want to achieve?
In case all you want simple timer, MTIM peripheral somehow more resembles simpler HC08 timers.

[Circlotron]

I just want to load the high and low counter byte into H:X then clear the counter, then repeat later. Just want a simple way to measure time between input pulses. HC08 was was easy peasy.

[Circlotron]

According to AN2717 "The HCS08 TPM also reduces the complexity of the M68HC08 TIM functions and improves the use of MCU resources." Yeah, right...

[Circlotron]

I would do this sort of thing repetitively with a HC08 in an engine ECU, measuring rpm and doing things accordingly. Why is something so simple now so hard???

Code: [Select]

TIMER_STUFF BRSET TOF,TSC,VERYTOP_X ;super slow! = 1.048560 sec, 28.6 rpm 4 cyl

LDHX TCNTH ;grab timer
BSET TRST,TSC ;reset timer
BCLR TOF,TSC ;reset overflow if set
STHX TBS_MSB ;for offtime calc
STHX TBSDIV8_MSB ;for excess dwell calc
STHX STEP_MSB ;for excess dwell step size
CPHX #6250 ;go back to cranking mode
BHI VERYTOP_X ;if < 300 rpm 4 cyl

[DDunfield]

----
12.4.3.4 Counter reset

Any write to CNTH or CNTL register resets the FTM counter to the value of 0x0000 and
the channels output to its initial value, except for channels in output compare mode.
----

EDIT: That was from the 9S08PL16 manual which I had handy and assumed it would be the same... it ain't.

From the 9S09PA16 manual:

----
12.4.3.4 Counter reset

Any write to CNTH or CNTL register resets the FTM counter to the value of CNTINH:L
and the channels output to its initial value, except for channels in output compare mode.
----

So on the PA16 you need to write zeros to initial value registers first. Then any write to CNTH or CNTL will reset the timer to zero.

Dave

[jaromir]

TPM, being discussed in AN2717 is different to (actaully subset of) FTM.

Once the timer is running (CLKS and PS bits in SC register are set to reasonable value), you can read out the CNTH/CNTL, then writing anything to CNTH/CNTL will trigger transfer from CNTINH/CNTINL registers (that can be kept zero-ed all the time) and contiune running. Does this work for you?

[Circlotron]

^^ Almost midnight here. I'll try tomorrow. Thanks.

Edit -> still another 8 hours till I can try this, but it looks like the answer.
A big part of the problem was that I was looking how to reset the TIMER rather than the COUNTER.

[Circlotron]

Looking again now.
Another difficulty...
In 12.3.2 Register descriptions, Counter Initial Value High (FTM0_CNTINH) is shown as being at $37 absolute, but the programming algorithm shows $30 to $3A as being unimplemented and table 4-3 shows that range as reserved. Lucky I don't need to read or write to it because it is zero at reset.

In 12.3.11 is shows FTMx_CNTINH as being at Base address + 17h offset. What does that mean? What is base address?

Furthermore, 12.3.2 Register descriptions shows Channel Status and Control (FTM0_C2SC) at $2B but table 4-3 shows $2B as reserved.


One good thing, STA  FTM0_CNTH  clears the counter just fine. Hooray for that at least.