Author Topic: about verilog,what is meaning of if(!res_n) (Read 1758 times)

david-IT · « **on:** March 24, 2016, 09:14:45 am »

Reg[17:0] cnt;
always@(posedge clk)
if(!rst_n)
cnt<=18'd0;
else
cnt<=cnt+1'b1;

What is the meaning of if(!res_n)?

david-IT · « **Reply #1 on:** March 24, 2016, 09:52:26 am »

don't tell me no one knows here

Codemonkey · « **Reply #2 on:** March 24, 2016, 10:02:42 am »

It translates to "if res_n signal is low"

david-IT · « **Reply #3 on:** March 24, 2016, 10:26:43 am »

It translates to "if res_n signal is low"

thanks for reply,i think i am a little understand now

Scrts · « **Reply #4 on:** March 24, 2016, 07:41:02 pm »

It translates to "if res_n signal is low"

Just for the reference: ! means "not". So it translate if rst_n is NOT high or, as being said, if rst_n is low.

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