Author Topic: Verilog and VHDL Regionalism  (Read 6303 times)

0 Members and 1 Guest are viewing this topic.

Offline Legion

  • Frequent Contributor
  • **
  • Posts: 357
Verilog and VHDL Regionalism
« on: May 21, 2014, 07:05:41 pm »
I've read over and over how Verilog is more popular in North America and VHDL is more popular overseas. How did that happen? I can't think of any software language analogs, ie. "C is more popular in the US, but Pascal dominates Europe."
 

Offline legacy

  • Super Contributor
  • ***
  • !
  • Posts: 4415
  • Country: ch
Re: Verilog and VHDL Regionalism
« Reply #1 on: May 21, 2014, 07:27:25 pm »
dunno, i can't provide a reasonable motivation, i can only see that there are different tools for them, for example SIGASI is a vhdl editor, it is not a verilog editor (and they do not want to support verilog at all), also the "VHDL_direct" (by Green Mountains)  is specific for VHDL and not for verilog, the opposite is happening for other tools and for other books which are telling you examples ONLY for verilog (fpga by design, fpga real world, and books like that)  :-//
 

Offline miguelvp

  • Super Contributor
  • ***
  • Posts: 5549
  • Country: us
Re: Verilog and VHDL Regionalism
« Reply #2 on: May 22, 2014, 01:48:37 am »
I do prefer VHDL over Verilog but SystemVerilog seems to be the new upcoming candidate:

http://en.wikipedia.org/wiki/SystemVerilog

I haven't tried it yet though.
 

Offline Bassman59

  • Super Contributor
  • ***
  • Posts: 1524
  • Country: us
  • Yes, I do this for a living
Re: Verilog and VHDL Regionalism
« Reply #3 on: May 22, 2014, 06:40:34 pm »
I've read over and over how Verilog is more popular in North America and VHDL is more popular overseas. How did that happen? I can't think of any software language analogs, ie. "C is more popular in the US, but Pascal dominates Europe."

I've been hearing this forever, and I'm pretty sure it's bullshit.
 

Offline suicidaleggroll

  • Super Contributor
  • ***
  • Posts: 1455
  • Country: us
Re: Verilog and VHDL Regionalism
« Reply #4 on: May 22, 2014, 06:49:23 pm »
I was born, grew up, went to college, and currently work in North America.  They taught VHDL to the EEs in college, and everybody I know in the industry uses VHDL.  In fact I have yet to meet anybody in person who uses Verilog.
 

Offline JoeyP

  • Frequent Contributor
  • **
  • Posts: 319
  • Country: us
Re: Verilog and VHDL Regionalism
« Reply #5 on: May 22, 2014, 08:27:07 pm »
I have to agree that it seems to be a misconception. I use, and virtually everyone that I know personally uses VHDL. I've been to classes provided by Altera, and despite the fact that Altera's tools for VHDL were quite inferior for a long time, most of the people in the classes still chose to use VHDL instead of Verilog.
 

Offline Balaur

  • Supporter
  • ****
  • Posts: 525
  • Country: fr
Re: Verilog and VHDL Regionalism
« Reply #6 on: May 22, 2014, 09:43:04 pm »
I worked quite a lot in design verification and most designs and obviously testbenches were in Verilog.

However, the most recurring design that I've used through my career is the Leon CPU and its various versions. That one is in VHDL.
 

Offline Scrts

  • Frequent Contributor
  • **
  • Posts: 658
  • Country: lt
Re: Verilog and VHDL Regionalism
« Reply #7 on: May 23, 2014, 08:03:46 am »
They used Verilog is ASIC designs mostly I think. E.g. they use SystemVerilog now on such GPUs like nVidia ones. Not sure, but I've seen an article somewhere. Or maybe a job post with these requirements...
 

Offline legacy

  • Super Contributor
  • ***
  • !
  • Posts: 4415
  • Country: ch
Re: Verilog and VHDL Regionalism
« Reply #8 on: May 23, 2014, 08:12:51 am »
I worked quite a lot in design verification and most designs and obviously testbenches were in Verilog.

why they prefer Verilog ?
 

Offline Dago

  • Frequent Contributor
  • **
  • Posts: 657
  • Country: fi
    • Electronics blog about whatever I happen to build!
Re: Verilog and VHDL Regionalism
« Reply #9 on: May 23, 2014, 09:09:41 am »
I've read over and over how Verilog is more popular in North America and VHDL is more popular overseas. How did that happen? I can't think of any software language analogs, ie. "C is more popular in the US, but Pascal dominates Europe."

I've been hearing this forever, and I'm pretty sure it's bullshit.

I have the opposite feeling. I do not know a single place doing FPGA stuff in Finland or Europe who uses Verilog. VHDL exclusively. But based on these forums it seems the US people almost exclusively use Verilog. Kinda weird since VHDL is originally based on a US military standard.
Come and check my projects at http://www.dgkelectronics.com ! I also tweet as https://twitter.com/DGKelectronics
 

Offline Bassman59

  • Super Contributor
  • ***
  • Posts: 1524
  • Country: us
  • Yes, I do this for a living
Re: Verilog and VHDL Regionalism
« Reply #10 on: May 23, 2014, 05:41:56 pm »
But based on these forums it seems the US people almost exclusively use Verilog.

Except that's not true; I do VHDL at my current gig.

In my career, I've done both. I suppose that at some point, every company has to flip a coin and choose an HDL.
 

Offline free_electron

  • Super Contributor
  • ***
  • Posts: 7463
  • Country: us
    • SiliconValleyGarage
Re: Verilog and VHDL Regionalism
« Reply #11 on: May 23, 2014, 06:02:26 pm »
As i work in an international company : european designers are all vhdl , while all the stuff we do in the us is indeed verilog.

In the end it doesn't matter. everyone is responsible for a block. if they synthesize they synthesize. there are translator tools and the synthesizers like synopsys don;t care. they eat anything.

Verilog requires a lot less keyboard pounding than VHDL.

There are contests between VHDL and Verilog. you get a problem and 30 minutes to code it. VHDL always fails in these contests ( they are organised by the Synopsis users group). The veriloggers finish design and testbench while the VHDLlers are still stuck correcting the typo's in their source... to get it to synthesize.

i personally hate VHDL because some of the required keyboard pounding and a couple of really annoying things like having to create intermediate signals. if x is defined as an output you cannot write x = x+1 as you can't directly read from the output. that is simply stupid.

Verilog was always designed as a language to model logic from the beginning..
VHDL was an afterthough bolted on to HDL. HDL can be used to describe anything , analog , digital , mechanical , system assemblies. as long as you create definitions you can do anything. that is why , when writing logic you need to load those two IEEE libraries. those files define what is a logic one , what is a zero , what is an unknown , what is a tristate , weak pull up and their interrelations. it also describes to operators and their relationship. without those libraries HDL does not know about logic. there are libraries for analog , even to describe how two piece of metal are bolted together with a screw.
Professional Electron Wrangler.
Any comments, or points of view expressed, are my own and not endorsed , induced or compensated by my employer(s).
 

Offline djacobow

  • Super Contributor
  • ***
  • Posts: 1066
  • Country: us
  • takin' it apart since the 70's
Re: Verilog and VHDL Regionalism
« Reply #12 on: May 23, 2014, 06:19:34 pm »
But based on these forums it seems the US people almost exclusively use Verilog. Kinda weird since VHDL is originally based on a US military standard.

Ah, I think you do not understand the American mind, if you think engineers will be attracted to military standards.  I started my HDL career in VHDL. This was a long time ago. It felt like the worst bondage and torture that Nicholas Wirth could ever dream up. (Pascal => Ada => VHDL, direct lineage, all very European, by the way) In particular I remember that the VHDL compiler's parsers were brutally bad and could not generate an error message that pointed within 200 lines of the actual source of the error. This was with the MGC tools in the early 90s. I can only imagine the situation has improved since then.

Later, I went to work at Intel (where they were using iHDL at the time -- a lovely little streamlined if hacked-together language) and then switched to Verilog, and it was a breath of fresh air. It felt so pared down and simple. And it was so easy to link in C code, which was very helpful for testbenches, checkpointing memories and stuff like that. I'm sure you could do it with VHDL, but it wasn't as easy. Oh, and in performance terms, Verilog sims just flew compared to VHDL.

The one thing I preferred about VHDL was the "generate" statement, which allowed one to pretty easily assemble arrays of stuff "structurally." I believe Verilog has it now.

I don't do logic design anymore. I suspect the languages capabilities are more or less the same these days, but VHDL will always have a lot more words to type.
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 19839
  • Country: nl
    • NCT Developments
Re: Verilog and VHDL Regionalism
« Reply #13 on: May 23, 2014, 06:47:14 pm »
As i work in an international company : european designers are all vhdl , while all the stuff we do in the us is indeed verilog.

In the end it doesn't matter. everyone is responsible for a block. if they synthesize they synthesize. there are translator tools and the synthesizers like synopsys don;t care. they eat anything.

Verilog requires a lot less keyboard pounding than VHDL.

There are contests between VHDL and Verilog. you get a problem and 30 minutes to code it. VHDL always fails in these contests ( they are organised by the Synopsis users group). The veriloggers finish design and testbench while the VHDLlers are still stuck correcting the typo's in their source... to get it to synthesize.
IMHO this says more about the 'VHDL people' participating in the contest than VHDL. A lot of people don't use the power VHDL offers. Many times I see people using a case statement and lots of lines for a simple mux where all you need is output=array_of_signals(select);
« Last Edit: May 23, 2014, 06:57:50 pm by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline magetoo

  • Frequent Contributor
  • **
  • Posts: 284
  • Country: se
Re: Verilog and VHDL Regionalism
« Reply #14 on: May 23, 2014, 11:22:01 pm »
I can't think of any software language analogs, ie. "C is more popular in the US, but Pascal dominates Europe."

I have always believed that your software analog was actually kind of true.  Or rather, that Pascal-family languages were popular in German speaking countries.  (Has anyone else ever used Modula-2 or Oberon?)
 

Offline Neilm

  • Super Contributor
  • ***
  • Posts: 1462
  • Country: gb
Re: Verilog and VHDL Regionalism
« Reply #15 on: May 26, 2014, 06:26:03 pm »
  (Has anyone else ever used Modula-2 or Oberon?)

The introduction to programming course I had at university was Topspeed Modula-2. I think this is the first time any one has ever mentioned it.
Two things are infinite: the universe and human stupidity; and I'm not sure about the the universe. - Albert Einstein
Tesla referral code https://ts.la/neil53539
 

Offline Bassman59

  • Super Contributor
  • ***
  • Posts: 1524
  • Country: us
  • Yes, I do this for a living
Re: Verilog and VHDL Regionalism
« Reply #16 on: May 28, 2014, 10:44:34 pm »
As i work in an international company : european designers are all vhdl , while all the stuff we do in the us is indeed verilog.

In the end it doesn't matter. everyone is responsible for a block. if they synthesize they synthesize. there are translator tools and the synthesizers like synopsys don;t care. they eat anything.

Verilog requires a lot less keyboard pounding than VHDL.

There are contests between VHDL and Verilog. you get a problem and 30 minutes to code it. VHDL always fails in these contests ( they are organised by the Synopsis users group). The veriloggers finish design and testbench while the VHDLlers are still stuck correcting the typo's in their source... to get it to synthesize.
IMHO this says more about the 'VHDL people' participating in the contest than VHDL. A lot of people don't use the power VHDL offers. Many times I see people using a case statement and lots of lines for a simple mux where all you need is output=array_of_signals(select);

Yup, I agree.

Also, a good editor helps, and by "good editor," I mean emacs and its vhdl-mode.

Oh, yeah, there's the old joke: With VHDL, the compiler finds your errors. With Verilog, your customers find your errors.
 

Offline hans

  • Super Contributor
  • ***
  • Posts: 1081
  • Country: nl
Re: Verilog and VHDL Regionalism
« Reply #17 on: May 30, 2014, 09:02:44 am »
As i work in an international company : european designers are all vhdl , while all the stuff we do in the us is indeed verilog.

In the end it doesn't matter. everyone is responsible for a block. if they synthesize they synthesize. there are translator tools and the synthesizers like synopsys don;t care. they eat anything.

Verilog requires a lot less keyboard pounding than VHDL.

There are contests between VHDL and Verilog. you get a problem and 30 minutes to code it. VHDL always fails in these contests ( they are organised by the Synopsis users group). The veriloggers finish design and testbench while the VHDLlers are still stuck correcting the typo's in their source... to get it to synthesize.

i personally hate VHDL because some of the required keyboard pounding and a couple of really annoying things like having to create intermediate signals. if x is defined as an output you cannot write x = x+1 as you can't directly read from the output. that is simply stupid.

Verilog was always designed as a language to model logic from the beginning..
VHDL was an afterthough bolted on to HDL. HDL can be used to describe anything , analog , digital , mechanical , system assemblies. as long as you create definitions you can do anything. that is why , when writing logic you need to load those two IEEE libraries. those files define what is a logic one , what is a zero , what is an unknown , what is a tristate , weak pull up and their interrelations. it also describes to operators and their relationship. without those libraries HDL does not know about logic. there are libraries for analog , even to describe how two piece of metal are bolted together with a screw.

One key thing that never seems to be mentoined between VHDL and Verilog is that the one is strong typed and the other one is not.

If you're design an ASIC or silicon, you need to be goddamn know well what you're doing & typing, and what that (intermediately) translates to, when you're doing Verilog. I've learned VHDL first and wanted to learn the Verilog "dialect", but was immediately put off by this. It reminds me back in the old days I was writing PHP and Python, where there is no consistent way of telling what is what, or what output is yielded from which operation (and whether the types are consistent & correct).

An example: if I have a std_logic_vector which I want to "Cut up and paste together" , I can write something like this:

my_vector_2 <= my_vector_1(7 downto 1) & "00";

Great I've zero-ed the 2 LSB bits of that byte. If I put 1 bit too less or too much on this new vector, VHDL will prompt an error and say that the widths don't match.

In my little experience with Verilog, it didn't say that for me, and that implicit typing means you can do some really messy things, or miss bugs, or require extra synthesis steps to find out bits are undefined. It may be what you want if you're very experienced & clever, but for all other purposes I like the toolchain to point me at things even if it means I'm treated like a baby-coder.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf