Author Topic: ARM: SAMD51, Mainclock Reg APBDMASK not accepting settings?  (Read 472 times)

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Offline XFDDesign

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Sorry to bother, but this is rather irritating me: I have an ATSAMD51, and am looking to get a timer (TC6) setup. TC6 is tied to the Main Clock peripheral's (0x40000800) APBDMASK register (0x40000820). In order to enable TC6, I need to enable the clock resource. Per the usual gamut, I also have to setup the GCLK resource through the PCHCTRL register (39). Pretty standard stuff, which I've done for SERCOM resources and the like.

The problem I get is, MCLK->APBDMASK refuses to accept any settings except setting SERCOM4 and SERCOM5 to 1 (enabling them). SERCOM6 and SERCOM7 bits do not take. I cannot set any other bits of MCLK->APBDMASK and get it to stick. I did a number of reality checks:
- No error in my peripheral mapping, APDBMASK is correctly at 0x4000820 (MCLK + offset of 0x20).
- APDBMASK is not write-protected per the PAC
- I changed the ordering of PCHCTRL to before the mask enabling, and still nothing (just in case)
- I have not found anything in the datasheet specifically on APBDMASK which suggests special clock routing or setup

The short code snippet is:
   pMCLK->APBAMASK.bits.SERCOM0 = 1;      // enable SERCOM0 peripheral
        pGCLK->PCHCTRL[7].bits.GEN = 2;         // use Generator 2 for it
   pGCLK->PCHCTRL[7].bits.CHEN= 1;         // turn on the peripheral channel for SERCOM0

   pMCLK->APBDMASK.bits.TC6 = 1;                      // enable TC6 peripheral
   pGCLK->PCHCTRL[39].bits.GEN = 2;                  // route GEN2 to TC6
   pGCLK->PCHCTRL[39].bits.CHEN = 1;             // enable it

What gets more bizzare to me, is that this behavior mirrors itself on APBCMASK. But once you get to APBAMASK and APBBMASK, they work just fine.

GCLK0 and GCLK2 share the same input resource, a 12MHz external oscillator. Everything outside of this affair works just fine.

Does anyone have some ideas on what I'm doing wrong, or where I should look?
 

Offline ataradov

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Re: ARM: SAMD51, Mainclock Reg APBDMASK not accepting settings?
« Reply #1 on: July 19, 2019, 02:02:33 am »
What is the full part number of the device you have?  QFN-48 parts only have 4 TCs, for example.
Alex
 

Offline XFDDesign

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Re: ARM: SAMD51, Mainclock Reg APBDMASK not accepting settings?
« Reply #2 on: July 19, 2019, 11:56:27 am »
What is the full part number of the device you have?  QFN-48 parts only have 4 TCs, for example.
You know, that's it and thus why I'm a moron. (It is a QFN48 on this project: SAMD51G19A )

Thank you.
 

Online westfw

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Re: ARM: SAMD51, Mainclock Reg APBDMASK not accepting settings?
« Reply #3 on: July 20, 2019, 06:44:43 am »
Heh.  It is interesting to have actual code show that the 48pin chip is actually different, and not just the same die in a smaller package...

 

Offline ataradov

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Re: ARM: SAMD51, Mainclock Reg APBDMASK not accepting settings?
« Reply #4 on: July 20, 2019, 06:47:49 am »
Heh.  It is interesting to have actual code show that the 48pin chip is actually different, and not just the same die in a smaller package...
But it is though. There are settings programmed in production to tell the chip what it is.

But even on the chips where there are no settings, functionality of those "extra" blocks is not guaranteed. There may be a die cut in the future that will cut them for real.
Alex
 


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